The portion of the Security Monitor which is only on while the SoC is powered is referred to as the High Power (HP) section; the battery-backed portion is referred to as the Low Power (LP) section, and the TA_BB_VDD pin is the power supply to the LP section.
TA_BB_VDD should be connected to a power management IC (PMIC) which supplies 0.9 V or 1.0 V (same as VDD) from system power while the system is on, and switches to the supply source to a battery when the system is powered off.
There are special power sequencing and clocking requirements when using the battery-backed Security Monitor features on Trust 2.1 devices. Specifically, before allowing VDD to ramp up to the 0.5 V level, ensure that:
• OVDD has ramped to the recommended operational voltage
• DIFF_SYSCLK/DIFF_SYSCLK_B is running. This clock pair should have a minimum frequency of 800 Hz and a maximum frequency no greater than the maximum supported system clock frequency for the device.
Use of the LP section is optional.
If a Zeroizable Master Key or monotonic counter aren’t required to meet system trust objectives, TA_BB_VDD should be connected to VDD.
