SGMII connection with Marvel Phy

cancel
Showing results for 
Search instead for 
Did you mean: 

SGMII connection with Marvel Phy

50 Views
rashmikj
Contributor II

We have a custom board set up with the a LS1046a processor. The serdes control section of the rcw is configured as 0x1133 and the serdes1 port A and port B is connected to the SGMII interface of a Marwell 88E1512 Phy chip similar to LS1046ardb Kit.

The phy addres of the two phys are 1 and 0 and we modified accordingly in device tree file of LS1046ardb mdio@fd000  

Only difference is it is connected to EMI2_MDC/MDIO . So we modified device tree as follow.

But there is no link when we connect copper cable to SGMII Phy.

0 Kudos
3 Replies

43 Views
yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following to modify the dts file. In addition, please use the default Kernel configuration file provided in LSDK.

mdio@fc000 {
rgmii_phy1: ethernet-phy@1 {
reg = <0x1>;
};

rgmii_phy2: ethernet-phy@0 {
reg = <0x0>;
};

};

mdio@fd000 {

sgmii_phy1: ethernet-phy@1{
reg = <0x1>;
};

sgmii_phy2: ethernet-phy@0 {
reg = <0x0>;

};

You could check whether the Ethernet link is available in u-boot.

Please modify u-boot source code board/freescale/ls1046ardb/eth.c as the following.

/* Set the two on-board SGMII PHY address */

        fm_info_set_phy_address(FM1_DTSEC5, SGMII_PHY1_ADDR);

        fm_info_set_phy_address(FM1_DTSEC6, SGMII_PHY2_ADDR);

Modify to =>

        fm_info_set_phy_address(FM1_DTSEC5, 1);

        fm_info_set_phy_address(FM1_DTSEC6, 0);

       

dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++)
fm_info_set_mdio(i, dev);

/* XFI on lane A, MAC 9 */
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(FM1_10GEC1, dev);

Modify to =>

        dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);

        fm_info_set_mdio(FM1@DTSEC3, dev);

       fm_info_set_mdio(FM1@DTSEC4, dev);

 

        dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);

        fm_info_set_mdio(FM1_DTSEC5, dev);

        fm_info_set_mdio(FM1_DTSEC6, dev);

Then run the following command to check whether you could get similar information.

=> mdio list
FSL_MDIO0:
1 - RealTek RTL8211F <--> FM1@DTSEC3
2 - RealTek RTL8211F <--> FM1@DTSEC4
FM_TGEC_MDIO:
1 - RealTek RTL8211F <--> FM1@DTSEC5
0 - RealTek RTL8211F <--> FM1@DTSEC6
=>

Then execute the following command to check the link status.

=> mdio read FM1@DTSEC5 1
Reading from bus FSL_MDIO0
PHY at address 1:
1 - 0x798d

The link partner (“copper side”) link status bit is in Register #1 on the PHY. The 'Link Status' bit is bit #2 (from the left) of the last nibble. In the above example the nibble of interest is "d" (d = b'1101'), and therefore the 'Link Status' = 1, which means
'link up'. If the link were down this bit would be a "0," and we would see 0x7989.

0 Kudos

32 Views
rashmikj
Contributor II
Iam getting following log message in uboot. Could not get PHY for FM_TGEC_MDIO: addr 1 Failed to connect Could not get PHY for FM_TGEC_MDIO: addr 0 Failed to connect
0 Kudos

23 Views
yipingwang
NXP TechSupport
NXP TechSupport

Please refer to the following section in Ethernet Management Interface (EMI1/2) pin termination checklist.

EMIx_MDC could be left unconnected since it is an output.

  

yipingwang_0-1617850803602.png

 

     

yipingwang_1-1617850804480.png

 

 

0 Kudos