Regarding POR settings of P1013

[rinkutakkar]

We are driving the POR signals of P1013 from lattice cpld LCMXO2-1200UHC as follows : -

cfg_sys_pll <= "011";
cfg_ddr_pll <= "010";
cfg_core0_pll <= "100";

cfg_core1_pll <= "100";
cfg_rom_loc <= "1110";
cfg_serdes_ports <= "10111";
cfg_ddr_speed <= '0';
cfg_srds2_refclk <= '0';
cfg_elbc_ecc  <= '0';
cfg_tsec1_port <= '1';
cfg_tsec2_port <= '0';
cfg_plat_speed <= '1';
cfg_core0_speed <= '1';

We have asserted the hreset signal for around 125 us and maintained a set up time of 100 us and hold time of 2 sysclk cycles(30 ns) for POR signals with respect to deassertion of hreset signal. PFA the simulation snapshot for the same,

Observation:-

Processor is being detected using lauterbach debugger cable but in target reset fails and when we try to read the bootstrap configuration it shows bus error. Following commands have been used for the same:-

system.detect cpu

system.memaccess cpu

system.mode attach

per , "global utility tool , power-on" /dualport

We have also probed the asleep signal . It is being driven high and then negated. As per the reference manual (pg148)  this happens when the processor properly initializes after a POR sequence.

So we are confused whether the POR setting is wrong or the timing is incorrect or any other issue. Kindly guide.

[rinkutakkar]

Please find below few more observations:-

1. We are able to view the POR settings via the lauterbach trace32 debugger only if the HRESET signal is being asserted for around 20-30       SYSCLK cycles during power up(and all the POR settings are correct). It shows bus error if the assertion time of HRESET signal is increased. 

2. When we try to reset the processor using cop_hreset signal via the debugger, it shows "debug port fail" error. This is invariant of the             assertion time of hreset signal.

Kindly suggest how to proceed further.

[rinkutakkar]

Thanks for your valuable comments!!

Processor is properly detected with the lauterbach debugger cable so we are assuming that the JTAG  path is through. Voltage levels of all POR signals are also within the specified range levels of LVCMOS33. JTAG connection circuit is as per the design checklist.

[rinkutakkar]

Thanks for your response!!!

HRESET and configuration signals are driven synchronously with respect to sysclk. We have tried to configure the set up time and hold time as 5 sysclks and 3 sysclks respectively but it does not work.We have also verified the configuration signals using logic analyzer.

kindly guide

[ufedor]

> We have also verified the configuration signals using logic analyzer.

Use a digital scope and check POR levels of each configuration signal.

> We have asserted the hreset signal for around 125 us

Minimum /HRESET assertion time is 600 us - refer to the processor's HS, Table 6. RESET initialization timing specifications.

[rinkutakkar]

We are also analyzed the signals using digital scope. Values seems fine as per our requirement . We also tried to change the assertion time of hreset signal to 600 us but it didnt work.

[ufedor]

> We are also analyzed the signals using digital scope.

Please provide measured voltage levels for POR configuration signals representing the following groups:

cfg_sys_pll <= "011";
cfg_ddr_pll <= "010";
cfg_core0_pll <= "100";

Ensure that JTAG connection circuit is implemented as described in the AN4534 - P1010 Design Checklist, Figure 2. JTAG Interface Connection.

Doublecheck POR leveles of all signals having note 7 in the P1010 HS, Table 1. P1010 pinout listing.

[ufedor]

> cfg_sys_pll <= "011";

To check that all configuration signals are correctly assigned and driven please use a digital scope and check POR levels of each configuration signal.

> We have asserted the hreset signal for around 125 us

Minimum /HRESET assertion time is 600 us - refer to the processor's HS, Table 6. RESET initialization timing specifications.

> maintained a set up time of 100 us and hold time of 2 sysclk cycles(30 ns) for POR signals

Are /HRESET and configuration signals driven synchronously with SYSCLK?

Try to configure POR configuration signals setup for 5 SYSCLKs and hold for 3 SYSCLKs.