PCIe x4 connections to LS1021A

[fzhang]

Using LS1021A to communicate with FPGA (Arria V) through PCIe x4 bus. Is there a reference design or example for PCIe x4 connections to LS1021A? I am checking the reference manual.

Any responses are appreciated.

[alexander_yakov · Accepted solution]

We do not offer "reference schematics", but we offer schematics from our LS1021A-based development boards to use as reference. Please create a support case to online technical support and request LS1021A-based development board schematic with PCIe x4 slot.

How I could create a Service Request? 

Have a great day,
Alexander

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[fzhang]

Thank you, Alex.

I submitted the request. That will save me a lot of time.

[fzhang]

All the data lanes are pretty clear. But need help on those control, reset, and reference clock pins below:

Thank you!

[fzhang]

Found this really helpful:

http://read.pudn.com/downloads166/ebook/758109/PCI_Express_CEM_1.1.pdf