P2020 DMA over PCIE to FPGA

[nickangelo]

Does using the P2020 DMA (targeting PCIE) produce Memory Write TLPs with payload greater than 4bytes? Say 128bytes up to 512bytes?

Thanks!

[r8070z]

Have a great day,

The P2020 DMA supports up to 256 bytes for sub-block transfers to maximize performance.

The P2020 PCIe max payload is 256 bytes too. Hence the P2020 DMA (targeting PCIE) may produce Memory Write TLPs with payload greater than 4bytes. Say 128bytes but not 512bytes.

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[nickangelo]

Thanks for the reply!

When you say "may produce" are there cases where it will take a buffer and chop it up into TLPs with 4bytes payload rather than bursting a single TLP with max payload size (say 256 bytes in this case)?

The reason I am asking for these details is because the P2020 is connected to an FPGA and I need to know how to design the FPGA to handle the data correctly, unfortunately the boards are not in-house yet, so I can not get on the CPU and try it.

[r8070z · Accepted solution]

The DMA controller may issue smaller transactions from the source and destination

address engines in an effort to reach alignment for improved performance.

In the P2020 reference manual (P2020RM) Figure 13-277. Source/destination engine transaction size flow chart

shows the decision points made in determining the transaction size. It also provide demo:

For example, if BCR[BC]=512 bytes and MR[BWC]=256 bytes, reading from starting

address 0x5D0 will result in the following transaction sizes:

-- Channel arbitration --

0x5D0 - 16 bytes

0x5E0 - 32 bytes

0x600 - 128 bytes

0x680 - 64 bytes

0x6C0 - 16 bytes

-- Channel arbitration --

0x6D0 - 16 bytes

0x6E0 - 32 bytes

0x700 - 128 bytes

0x780 - 64 bytes

0x7C0 - 16 bytes

[nickangelo]

Perfect! That's exactly what I wanted to know.

Thank You!