There is no known issue with the P2020 PCIe3 operating as x1.
I've doublechecked that this configuration is viable using P2020DS board and the cfg_io_ports[0:3]=0010.
Please also check the DEVDISR and refer to the P2020 QorIQ Integrated Processor Hardware Specifications, Table 1. P2020 Pinout Listing and check POR behavior of all signals having Note 15.
4) How exactly the lane 3 is connected?
It is possible to implement three x1 PCIe interfaces using P2020 when cfg_io_ports[0:3]=0b0010.
In this case PCIe3 has to use only lane 2 and lane 3 has to be terminated as unused referring the AN4261 - P2020 Design Checklist.