According to QorIQ LS1043A Reference Manual, Rev. 3, 02/2017, Table 4-14., the CGA_PLL2_SPD bit in RCW should be set to 1 for PLL2 frequencies from 800MHz to 1000.1 MHz):
but the RCW for LS1043A in SDK does not care about this bit and leave it to 0 even for 1000MHz PLL2. For example here:
sdk/rcw.git - Freescale PowerPC Reset Config Word (RCW) Tree
or:
rcw/rcw_1200.rcw at integration · qoriq-open-source/rcw · GitHub
I have verified RCW binaries generated from the above descriptions and there is really CGA_PLL2_SPD set to 0.
What do you recommend? Follow the Reference Manual or follow the SDK for 1000MHz PLL2 settings (for our custom board RCW)?
Thank You,
Cyril
已解决! 转到解答。
Setting the CGA_PLL2_SPD to 1 has serious impact on DPAA hardware or Linux SDK DPAA drivers. Ethernet frames (approximately 50% or more) received or transmitted from LS1043A RDB have garbled payload (typically one bit in a frame is flipped to 0), even if frame's FCS checked by mEMAC is OK. I have tested the behavior with the current LSDK 18.03. I have built the SD card image for LS1043A RDB and I have made only one change in the LSDK software -- CGA_PLL2_SPD set to 1 in u-boot file:
flexbuild/packages/firmware/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg:
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
08100010 0a000000 00000000 00000000
14550002 80004012 60040000 c1002400 # changed from 14550002 80004012 60040000 c1002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001
So, after all, I think the safe way is to stay with the NXP's LSDK settings.
I'm quite sure 1000 Mhz will work with both options, because it is just on the border. However, if the question is which way to follow, than - we recommend following our documentation. I will report this contradiction to our Linux team, thank you for pointing.
Have a great day,
Alexander
TIC
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Setting the CGA_PLL2_SPD to 1 has serious impact on DPAA hardware or Linux SDK DPAA drivers. Ethernet frames (approximately 50% or more) received or transmitted from LS1043A RDB have garbled payload (typically one bit in a frame is flipped to 0), even if frame's FCS checked by mEMAC is OK. I have tested the behavior with the current LSDK 18.03. I have built the SD card image for LS1043A RDB and I have made only one change in the LSDK software -- CGA_PLL2_SPD set to 1 in u-boot file:
flexbuild/packages/firmware/u-boot/board/freescale/ls1043ardb/ls1043ardb_rcw_sd.cfg:
#PBL preamble and RCW header
aa55aa55 01ee0100
# RCW
08100010 0a000000 00000000 00000000
14550002 80004012 60040000 c1002400 # changed from 14550002 80004012 60040000 c1002000
00000000 00000000 00000000 00038800
00000000 00001100 00000096 00000001
So, after all, I think the safe way is to stay with the NXP's LSDK settings.