LS1021a IFC Interface Addressing Problem

[emreanilterziog]

Hi,

We have a problem about LS1021a IFC interface's addressing mechanism. We want to use IFC interface to communicate with FPGA. We changed and added some lines of codes  on u-boot. When we tested we noticed that data was sending correctly but address data was always 0x6. We only connected first 3 pins of data pins A16-17-18 and we read values on chip scope as :

A16 - 1

A17 - 1

A18 - 0

Our send/read data command is mw.b/md.b 0x60000000 0x1 and our notes on this stage is:

• changing base address on u-boot doesn't change,
• changing sending or reading address used in mw/md command doesn't change 0x6 address value which reading from pins.

Could you please help us about this issue? I added our configuration below.

Thanks.

Our u-boot configuration:

/*
* IFC Definitions
*/
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE

#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
CSPR_PORT_SIZE_8 | \
CSPR_MSEL_GPCM | \
CSPR_V)
#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(512 * 1024 * 1024)
#define CONFIG_SYS_FPGA_CSOR (CSOR_GPCM_GPMODE_NORMAL | \
CSOR_GPCM_GPTO(256) | \
CSOR_GPCM_ADM_SHIFT(4) | \
CSOR_GPCM_TRHZ_20 | \
CSOR_GPCM_BCTLD)

/* CPLD Timing parameters for IFC GPCM */
#define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
FTIM0_GPCM_TEADC(0xf) | \
FTIM0_GPCM_TEAHC(0xf))
#define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
FTIM1_GPCM_TRAD(0x3f))
#define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
FTIM2_GPCM_TCH(0xf) | \
FTIM2_GPCM_TWP(0xff))
#define CONFIG_SYS_FPGA_FTIM3 0x0

#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_FPGA_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_FPGA_CSPR
#define CONFIG_SYS_AMASK0 CONFIG_SYS_FPGA_AMASK
#define CONFIG_SYS_CSOR0 CONFIG_SYS_FPGA_CSOR
#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_FPGA_FTIM0
#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_FPGA_FTIM1
#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_FPGA_FTIM2
#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_FPGA_FTIM3

Our RCW:

Reset Configuration Word (RCW):
       00000000: 0608000a 00000000 00000000 00000000
       00000010: 30000000 00007900 e0015a00 21046000
       00000020: 00000000 00000000 00000000 084bcf00
       00000030: 00000000 4704b540 00000000 00000000

[ufedor]

Please provide additional information as attachment:

1) the processor connection schematics

2) the IFC CCSR complete memory dump (using U-Boot 'md' command)

[emreanilterziog]

Hi,

1-)We use TQMLS1021A SoM which has pull-down resistor on IFC_A16 and pull-up on IFC_A17 according to its user manual. In addition, in our schematics, there are 10K pull-up resistors on IFC_CS0_B, IFC_RB0_B and IFC_PERR_B lines as you can see in the attached figures. We connect IFC_AD[0:7] , IFC_A16, IFC_A17, IFC_A18, IFC_CLK0, IFC_OE_B, IFC_CS0_B and IFC_WE0_B lines to both Altera MAX10 FPGA and backplane connector. Also the multiplexed pins between IFC and SPI1 interfaces are used as SPI pins and connected to an MRAM device. The remaining lines for IFC interface are left unconnected. I attached schematic figures.

2-) All ifc registers attached.

Thanks.

[ufedor]

Please provide complete schematics as searchable PDF (so it will be possible search for a signal name) - not a picture.

How do you plan to use IFC_AD[0:7] , IFC_A16, IFC_A17, IFC_A18 as address?

Please try to execute "mw.b 6FF00000 1" and check the address lines behaviour.

[emreanilterziog]

Hi Ufedor,

We can only provide this part of schematic but in this schematic document, there is only ifc related signals added. About your question, we only want to use IFC16-17-18 pins for addressing(small address space is enough for us). We tried "mw" command to write 0x6ff00000 and the output is same (you can find chip scope images in attached pdf). Actually our main problem is this situation we can only see 1,1,0 on this three address pins. We also change baseAddress to 0x70000000 on u-boot but nothing changed. We don't know what is the cause of the problem?

Have a nice day.

Emre.

[ufedor]

> We tried "mw" command to write 0x6ff00000 and the output is same

Please add IFC_AVD to the chip scope.

Disconnect the Altera FPGA (or left it in reset so all pins will be tri-stated) and provide traces for:

mw.b 6FF00000 1

mw.b 60000000 1

> We don't know what is the cause of the problem?

I need complete schematics as searchable PDF to inspect the IFC signals connection.