Interfacing 2 DDR4 (512 Meg x 16) discrete chips with T1040

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Interfacing 2 DDR4 (512 Meg x 16) discrete chips with T1040

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xarowubas
Contributor III

Hello,

I'm designing a custom board around T1040. Can I interface only 2 DDR4 (512 Meg x 16) discrete chips with 64 bit DDR controller of T1040. As these two x16 chips will require 32 bit data bus so remaining 32 bits of DDR Controller will be No Connect. Will this cause problem?

Thanks,

Xaro

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ufedor
NXP Employee
NXP Employee

T1040 DDR controller supports 32-bit data bus - refer to the QorIQ T1040 Reference Manual, 14.2 DDR Features:

"• Data bus widths supported:
• 64-/72-bit
• 32-/40-bit"

Also please refer to the AN4825 - T1040 Family Design Checklist, Table 9. DDR controller pin termination checklist where it is stated that unused DDR interface signal can be left unconnected.

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883件の閲覧回数
ufedor
NXP Employee
NXP Employee

T1040 DDR controller supports 32-bit data bus - refer to the QorIQ T1040 Reference Manual, 14.2 DDR Features:

"• Data bus widths supported:
• 64-/72-bit
• 32-/40-bit"

Also please refer to the AN4825 - T1040 Family Design Checklist, Table 9. DDR controller pin termination checklist where it is stated that unused DDR interface signal can be left unconnected.