In LS1043A, Please confirm the Clocking and Reset Sequence.
(Please correct if my understanding is wrong,)
Step 1: SYSCLK, DDRCLK needs to supplied before asserting PORESET is Asserted.
Step 2: After Desassertion of PORESET RCW data is loaded and HRESET is remain asserted.
Step 3: LS1043A PLLs (Platform, Core, other PLLs including SerDesPLL)begins to lock as per the setting in RCW data.
Step 4: HRESET is Deasserted.
My Actual doubt is does SerDes Reference clock(100MHz - PCIe and 100/156.25MHz- SGMII/XFI) need to be provided at which step of above sequence? or We shall provide SerDes Reference clock after deassertion of HRESET(STEP4)?
Hi,
I have a similar question regarding PCIe endpoint mode in LS1046A. In my case the PCIe endpoint port is driven by an external SerDes reference clock provided by a separate host system.
1) Is it allowed that the LS1046A boots up before the SerDes clock is available and stable?
2) If yes, will link training start automatically?
3) Will successful link training be reported to the endpoint driver as Link Up Detected (LUD) event/interrupt through register PEX_PF0_PME_MES_DR?
4) What happens if the SerDes clock goes away after the PCIe link has been established, e.g. host is restarted? Will a Link Down Detected (LDD) event be reported to software in this case?
5) Will link training start again once the SerDes clock is back?
Any clarification is appreciated!
Kind regards,
Friedrich
Have a great day,
The LS1043A reference manual says:
The detailed POR sequence for the device is as follows:
“1. The external system logic asserts PORESET_B and power is applied to comply with the chip's hardware specification data sheet .
…” and so on.
So before the SYSCLK power should be applied and PORESET is asserted. At that moment (3) the SerDes Reference clock also can be applied if the Serdes is used. Otherwise the SerDes Reference clock input can be connected to the GND. When serdes is used after completing reset, software should check the SerDesx_PLLnRSTCTL[RST_DONE] field to make sure that each active SerDes PLL on the device has locked.
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