I am trying to read data from the I2C bus with the MPC8544 acting as a slave.
I write 0x7e to the I2CADR (offset 0x000), 0x55 to the I2CDR (offset 0x010), and 0x81 to the I2CCR (offset 0x008).
If this is not the proper pseudo-assembly code sequence to set up the MPC8544 as a slave with addr 0x7e, what am I missing?
When I try a read using the SDA (I2C bus), I do not get out any data.
You are trying to set the device to be slave receiving mode? Are you expecting to receive a data addressed to 0x7e or broadcast? Are you observing SDA bus by oscilloscope or you are checking I2CDR?
You are trying to set the device to be slave receiving mode? yes
Are you expecting to receive a data addressed to 0x7e or broadcast? expecting to receive data of 0x55 (from I2CDR)
Are you observing SDA bus by oscilloscope or you are checking I2CDR? oscilloscope
Hello Thorne Kontos,
Please follow the procedure "11.5 Initialization/Application Information" in MPC8544RM(http://cache.freescale.com/files/32bit/doc/ref_manual/MPC8544ERM.pdf?fr=gdc) to configure configure I2C controller as slave(or master) mode.
I attached the I2C driver code from NetComm Software, please have a reference, especially pay attention to Initialization and Slave mode interrupt handler section.
Have a great day,
Yiping
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Hello,
That was helpful, but I still have a few questions. Remember I just want to treat the MPC8544 processor as a slave and read 1 byte of data out.
Under section 11.5.1 Initialization sequence...
Step 1 - All I2C registers located in a cache inhibited page - verified
Step 2 Update I2CFDR - done (wrote value of 0x02)
Step 3 Update I2CADR - done (wrote value of 0x7e)
Question
Can I now write the I2CDR register with the value of 0x55? I want to read this value out (after completing
the initialization sequence) over the I2C bus, with the MPC8544 transmitting this data after I query the slave address (I2CADR)
of 7e.
Step 4 Modify I2CCR - done (wrote 0x00)
Question
I am a bit confused about bit 3. Can you provide some clarification here? I want to read the value in I2CDR.
I also do not want to enable interrupts.
Step 5 Modify I2CCR again - done (wrote 0x80) to enable the I2C module
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Now here is what I am doing with the I2C bus...
Initiate START
9 SCL clocks SCA bus from off chip to MPC8544 slave
clks 1-7 address => 0111111
clk 8 read => 1
clk 9 if address matches, MPC8544 slave should drive this line LOW for the ACK (this isn't working!)
9 SCL clocks SCA bus from off chip to MPC8544 slave
clks 1-8 expect data from I2CDR of 0x55
clk 9 write 1 for NOACK
Do you see any problems with what I am doing here?
Thank you,
Thorne Kontos
Hello Thorne Kontos,
1. About I2CFDR, what is the desired SCL frequency, please refer to the application note https://cache.freescale.com/secured/32bit/doc/app_note/AN2919.pdf?__gda__=1411053926_5e2befed9086ea0...
2. Please check the value of I2C status register I2CSR at 9th clk.
Have a great day,
Yiping
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Note: If this post answers your question, please click the Correct Answer button. Thank you!
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