Regarding PORT_POL and PORT_ENA registers

キャンセル
次の結果を表示 
表示  限定  | 次の代わりに検索 
もしかして: 

Regarding PORT_POL and PORT_ENA registers

642件の閲覧回数
Amar1
Contributor I

What is the use of port-wise PORT_POLx and PORT_ENAx register, already we have different base address for the two GINT ports. What does it mean when we use GINT1_BASE->PORT_ENA[0]?

0 件の賞賛
返信
2 返答(返信)

602件の閲覧回数
Amar1
Contributor I

Thanks Edwin,

Got it and GINT is working fine.

0 件の賞賛
返信

620件の閲覧回数
EdwinHz
NXP TechSupport
NXP TechSupport

Hello @Amar1 

PORT_POLx register states the polarity of the pins in port “x” that will activate an interrupt. The PORT_ENAx register dictates which pins of the port will be enabled for an interruption and which won’t.

So, with GINT1_BASE->PORT_ENA[0], you are referring to the enable register of Port 0 with the Peripheral GINT1 base address. Here, you would assign a number based on the pins that you would like enabled for the interrupt.

If you would like more information about the polarity and enable registers, please refer to Chapter 21 of the User Manual (p. 398). Here’s the download link:

https://www.nxp.com/webapp/Download?colCode=UM11126

Also, you can find a GINT example on the SDK of your board of choice, under “driver_examples”.

 

Regards,

Edwin.

0 件の賞賛
返信