How to configure i.MX6DL's clk tree to get out of MX6QDL_PAD_GPIO_3__CCM_CLKO2 8KHz?

[zee_z]

How to configure i.MX6DL's clocking tree to get out of MX6QDL_PAD_GPIO_3__CCM_CLKO2 8KHz?

Presently, what I see using /sysfs is the following situation:

ssi2_sel 0 0 508235294 0 0
   ssi2_pred 0 0 127058824 0 0
      ssi2_podf 0 0 63529412 0 0
         ssi2 0 0 63529412 0 0
            cko2_sel 0 0 63529412 0 0
               cko2_podf 0 0 63529412 0 0
                    cko2 0 0 63529412 0 0 <<===== This one IIRC comes out of MX6QDL_PAD_GPIO_3__CCM_CLKO2

And for now it is almost 64MHz. Too high for me.

Any suggestions? I have no idea if this is possible.

What would be the lowest clock rate possible to get out of this pin? And how to achieve (how to configure the clocking tree), potentially using PLL4 (seems, PLL4 is not used presently)?

Thank you in advance,

Zee

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[igorpadykov]

Hi Zee

one can try to set CCM_CLKO2 frequency in uboot using sect.18.6.21 CCM Clock

Output Source Register (CCM_CCOSR)    i.MX 6Dual/6Quad Applications Processor Reference Manual

For "PLL4 as a source to the SSI2" one can look at Figure 18-2. Clock Tree - Part 1 and descriptions

in Chapter 18 Clock Controller Module (CCM)

Best regards
igor

[zee_z · Accepted solution]

Hotel skazat6, Igor, Ja nasel osibky vo NXP SW definicijah. Ja toze otlicno
boltaju po Russkij.

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Let me switch to English. I found the NXP bug. It is, I hope, not a silicon
bug, so here I will define some homework for the NXP BSP/Kernel team.

Here is the uneven situation (pll4 connected to the ssi2):

By theory, it should work like this:

pll4_post_div 0 0 262164000 0 0
pll4_audio_div 0 0 65541000 0 0 (divided by 4)

But, in reallity it works like this:

pll4_post_div 0 0 262164000 0 0
pll4_audio_div 0 0 131082000 0 0 (divided by 2)

By HW/silicon definition:

18.7.20 Miscellaneous Register 2 (CCM_ANALOG_MISC2n) NXP defined two-bit divider
(which divides by 4), but the function:

clk[IMX6QDL_CLK_PLL4_AUDIO_DIV] = clk_register_divider(NULL, "pll4_audio_div", \
"pll4_post_div", CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x170, 15, 1, \
0, &imx_ccm_lock);

Takes ONLY one bit, bit 15, into the account (MSB bit 23 of a DIV is masked). So,
the HW usage of the divider is limited by clumsy written kernel C code...

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Bottom line: faulty SW limits HW by dividing by two, which could lead to the
bogus limitations, without no needs!

Thank you for fixing this SW limitation in imx kernel in advance! Happy fixing
it for all of us!

Sincerely,

zee_z
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[zee_z]

One question more? Using PLL4 as a source to the SSI2, how far down to the minimum I can go with the PLL4? Seems to 24 MHz, given by hard coded design.

pll4_bypass_src 0 0 24000000 0 0 <<===== Can I go below this given minimum? And how low?
   pll4 0 0 147456000 0 0
      pll4_bypass 0 0 147456000 0 0
         pll4_audio 0 0 147456000 0 0
            pll4_post_div 0 0 36864000 0 0
               pll4_audio_div 0 0 36864000 0 0

include/dt-bindings/clock/imx6qdl-clock.h
236:#define IMX6QDL_PLL4_BYPASS_SRC        227

Thank you,

Zee

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