we want to ignore CD and CTS in HDLC mode on the MPC8309. There aren't port pins configureation registers as in the other MPC83xx devices.

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we want to ignore CD and CTS in HDLC mode on the MPC8309. There aren't port pins configureation registers as in the other MPC83xx devices.

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mikegreen
Contributor II

The other MPC83xx devices have port pin configuration registers to disconnect the pins and make them default active.  the MPC8309 only has the SICR_2 that sets the family of pins (TXD,RXD,RTS,CTS,CD) to HDLC.  what is the way in this device to make CTS and CD default active?

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mdmuazzam
Contributor III

Hi,

   I am also writing ucc7 for hdlc and my probles in that cts and cd are low.But i am not getting isr executed.

my interrupt number for 8309 board is 42 but after function irq_pasrse_and_map() i am getting same number.

do i need to configure GPIO fot getting interrupt,?

My sicr_2 value is 0.

Thanks

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alexander_yakov
NXP Employee
NXP Employee

No, there is no way to make CTS and CD pins permanently inactive in software for this processor.

For other processors we have a possibility to reconfigure these CTS and CD pins to other function, for example to GPIO, and in this case internal UCC' inputs CTS and CD will be internally connected to ground. This works for other processors with QE, for example MPC8360, but not for MPC8309. For MPC8309 there is no way to individually reconfigure CTS and CD pins to GPIO - all configuration for all five UCC pins is performed by one bit in SICR_2 register. There is also an option to enable internal pull-up for these pins, but no similar option for pull-down (active level for CTS and CD pins is "low") and no way invert active level.


Have a great day,
Alexander

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mikegreen
Contributor II

howdy Alexander Yakovlev

thank you for your response.

i would like to make sure that if we tie CTS and CD low this part will receive and transmit freely. i have tried grounding these pins and a loop back works fine. When it's used to talk to other devices there is no receive activity (nor errors in crc, ect..). is there a SICR_2 setting to allow this to operate freely?

the settings we are trying to use is SDLC (8 bit address, 16 bit crc).

thanks

Mike Green

Engineer

(281) 240-7233 x620

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