is MPC8260 brownout susceptible?

[tommctaggart]

Assuming that HRESET and PORESET are properly driven per data sheet requirements by external hardware, will the '8260 reliably recover from "brownout" conditions on either power supply rail (3.3V or 1.9V).

We know that some devices such as PLDs or FPGAs may have data sheet limitations on dips on the supply rails. We do not suspect a problem with the '8260 but are trying to determine if our power supply design is good enough. In our case, PORESET will reset the CPU whenever either rail is out of tolerance, and HRESET will release it from reset after a suitable delay following return of both rails to proper voltages.

Message was edited by: TOM MCTAGGART

[LPP]

MPC8260A provides strict requirments for power sequencing. Please refer to "MPC8260 PowerQUICC II Design Checklist " Section 2.3 Power Sequencing

http://cache.freescale.com/files/32bit/doc/app_note/AN2290.pdf

"

• VDD/VCCSYN—Must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.

• VDDH—Can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 msec. During normal operation, should not exceed VDD/VCCSYN by more than 2.0 V (HiP3) or 2.5V (HiP4).

• VIN—Must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

"

If the system power supply design does not control the voltage sequencing, the circuit made of Schottky diodes can be used to prevent undesired voltage configuration. This circuit would also manage "brownout" condition on either power supply rail (3.3V or 1.9V).

Have a great day,
Pavel

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