SDRAM continous Parity Error on MPC8270

[muhammadumersae]

Dear,

Following are specification of our board

CPU : MPC8270 (Big Endian)

Clock: Bus:100Mhz, Core: 400 Mhz

SDRAM: 64MB(Chip size) (13 rows, 11 columns, 4 banks, port: 8 bit) (Total Chips = 8) making 512MB total size

Issue: 
If we enable Data parity Pins (DP[0-7]), we get continuous parity errors which is reflected in TESCR registers. But the operating system is running fine (Showing no RAM corruption i.e. No parity error).

Interfacing:
We have interfaced data bus(inverted i.e. Big Endian style) as shown in attached file "Data_interface.PNG". While the Data parity pins (DP[0-7]) interfacing is not interfaced in Big endian Mode (Not inverted) i.e. DP0 is connected to D0 etc.

Questions:
(1) Is our interfacing for Parity is wrong? Should it be connected invertly i.e. DP0 connected to D7 etc.
(2) The parity error is generated but the core read/write transactions are good on SDRAM. Which means that

there is no parity error in SDRAMs. There must be some hardware interfacing issue. Is this approach right?

(3) What are the workarounds for this problem?

[muhammadumersae]

(Answer 2) => Following are the two cases of Data parity

(1) By porting operating system on SDRAM, the operating system works fine. Note that the if we enable the parity and also enable "Generate Exception on parity error". The operating system will halt.

(2) if we enable parity and disable "generate exception on parity error" the operating system works perfectly. Means that there is no parity error occurring(In reality). But by looking into "60x bus error registers" we can clearly say that the parity controller is continuously giving errors. System is not halted because we have disabled the exceptions.

(Answer 3) => SDRAM memory initialization sequence is same for all cases. Which works fine when parity exception is disabled and halts when parity exceptions are enabled

So if we conclude on that
(1) The parity error is not present in SDRAMs which we have checked by porting OS which is working fine. If there is some error exists in SDRAM then OS should generate exception (Like invalid instruction etc). OS does not generate exception even for a very long run.

(2) Parity Controller in MPC8270 is generating false parity errors, if we enable exceptions, system will halt and if we disable exceptions the system will not halt. Means that the parity controller is somehow generating wrong information.

So how to make parity controller work good?

[alexander_yakov]

Please specify the exact difference between "Parity disabled" and "Parity enabled" cases - which hardware registers you are modifying to enable Parity (and how), and how SDRAM memory initialization sequence is changed.

[muhammadumersae]

----------------------------------------
SDRAM parity initialization sequence
----------------------------------------

SDRAM parity Cases:

Note: Below is the case in which we will enable parity exceptions i.e. Setting EMCP bit of HID0 register.
In below case, the system will halt after calling (3)rd step i.e. Enable parity exceptions.

(1) SDRAM initialization sequence is as follows (SDRAM initialization sequence is always called first)

=> program MPTPR
=> Program PSRT
=> Program OR1
=> Program BR1
=> program PSDMR
=> Precharge all banks
=> issue 8 CBR refresh commands
=> Issue mode register command
=> Issue normal operation command

(2) Initialize the Data parity pins
=> clear EPAR bit in BCR (Bus configuration register) => Setting Odd parity
=> BR1[DECC] = 0x01 => Enable normal parity
=> SIUMCR[DPPC] = 0x01 => Enable data parity pins
=> SIUMCR[PBSE] = 0x1 => Enable PBSE
=> Clear TESCR1
=> Clear TESCR2

(3) Enable parity exceptions
=> vxHid0Set(vxHid0Get() | _PPC_HID0_EMCP) => Setting EMCP bit of HID0 register


---------------------------------------------------------------------------------------------------------------

Note: Below is the case in which we will not enable parity exceptions i.e. clear EMCP bit of HID0 register.
In below case, the system will not halt as we have not enabled the parity exceptions but the parity
error can be seen by looking into TESCR1 and TESCR2 registers.

(1) SDRAM initialization sequence is as follows (SDRAM initialization sequence is always called first)

=> program MPTPR
=> Program PSRT
=> Program OR1
=> Program BR1
=> program PSDMR
=> Precharge all banks
=> issue 8 CBR refresh commands
=> Issue mode register command
=> Issue normal operation command

(2) Initialize the Data parity pins
=> clear EPAR bit in BCR (Bus configuration register) => Setting Odd parity
=> BR1[DECC] = 0x01 => Enable normal parity
=> SIUMCR[DPPC] = 0x01 => Enable data parity pins
=> SIUMCR[PBSE] = 0x1 => Enable PBSE
=> Clear TESCR1
=> Clear TESCR2

[alexander_yakov]

You are using DECC=0x01 which means "Normal parity". To support normal parity, you have to use special "parity memory" with extra parity bit in each chip. The connection diagram you  submitted does not show parity memory, it shows just a common SDRAM chip connected to parity data bits and driven by PPBS. This will not work properly for operations less than port size. Please see application note AN2682 for more details.

https://www.nxp.com/docs/en/application-note/AN2682.pdf

[alexander_yakov]

1. All memory cells in memory chip are identical, so it is not important where you are storing any particular data bit. Therefore, this data reversal connection is not relevant to the error you observing.

2. You said the same memory works perfect in operating system - is this with parity enabled? If yes than I do not expect connection error.

3. Please check SDRAM memory initialization sequence and compare it with one, used in operating system. Understanding the difference between "good" and "bad" case is a key to debug the issue.

[muhammadumersae]

(Answer 2) => Following are the two cases of Data parity

(1) By porting operating system on SDRAM, the operating system works fine. Note that the if we enable the parity and also enable "Generate Exception on parity error". The operating system will halt.

(2) if we enable parity and disable "generate exception on parity error" the operating system works perfectly. Means that there is no parity error occurring(In reality). But by looking into "60x bus error registers" we can clearly say that the parity controller is continuously giving errors. System is not halted because we have disabled the exceptions.

(Answer 3) => SDRAM memory initialization sequence is same for all cases. Which works fine when parity exception is disabled and halts when parity exceptions are enabled

So if we conclude on that
(1) The parity error is not present in SDRAMs which we have checked by porting OS which is working fine. If there is some error exists in SDRAM then OS should generate exception (Like invalid instruction etc). OS does not generate exception even for a very long run.

(2) Parity Controller in MPC8270 is generating false parity errors, if we enable exceptions, system will halt and if we disable exceptions the system will not halt. Means that the parity controller is somehow generating wrong information.

So how to make parity controller work good?