MPC7448: Can L2I and L2HWF bit of L2CR be cleared by SW?

[Vivian1]

In the user manual MPC7450UM Table 2-12 (L2CR Field Descriptions) , there is description that "L2I is automatically cleared when the global invalidate completes.", it seems this bit is cleared by HW itself.

In the user manual MPC7450UM Section 3.6.3.1.1 and 3.6.3.1.4, it describes how to invalidate L2 cache. Here a setting L2I is worked in step 2 of section 3.6.3.1.1.

But I cannot find any description or clarification that what's the behavior when SW forces to clear this bit (for example, using an instruction "mtspr L2CR r3", here r3 is 0) .

So here comes the question, to make L2CR register as a known state during the reset (including hard reset and soft reset):

a. What's the default value of L2CR register when a soft reset (for a hard reset, its default value is 0x3000 0000 defined in table 2-45, but a soft reset value is not defined)?

b. What is the behavior when these L2I are cleared by SW? or Can L2I bit be cleared by SW?

c. For L2HWF, the similar question is raised, can this bit be cleared by SW?

[r8070z]

Yes clearing them in SW makes no sense.

[r8070z]

There is no need to clear bit like L2I or L2HWF in software (SW). SW (and only SW) can set this bit to initiate L2 hardware process. Then the SW can only check the completion of the process by polling this bit. On completion the bit will be cleared by hardware. As you can see from the manual, all operations with L2I/L2HWF bit setting followed by polling.

Soft reset does not affect L2 hardware, and thus there is no default L2CR value for a soft reset. The SW can read L2CR in order to recognize the L2 state.

[Vivian1]

Thanks for your professional response!

So does this mean that SW cannot clear these 2 bits (L2I, L2HWF) and clearing them in SW makes no sense, because these 2 bits from 1 to 0 is totally determined by hardware?