For MPC8541, when I am using a DDR controller with a 64-bit interface with a 32-bit memory sub system, which lanes should I use? When a 64-bit DDR interface is configured in a 32-bit data bus width, lanes [0:3] (MDQ [0:31]) will be used.

Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8536? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However external ODT is never enabled for SDRAM reads, this could lead to a conclusion that internal ODT is also affected by the TIMING_CFG_5 setting. Can you comment? TIMING_CFG_5 register is only for DRAM ODT (external ODT), this is verified and confirmed. As for your suggestion that because in most cases the read ODT on DRAM is off and hence it has something to do with internal ODT is not a valid assumption. The Read ODT for DRAM is an option available if required. In most cases it will not apply, but there may be a configuration that may require it and then the option is available for such users. Please clarify the meaning of TIMING_CFG_5 register for DDR3 controller of the MPC8536. The sentence ".. relevant ODT signal(s)" is common to all fields. What is this referring to? Is that both a) an internal signal controlling internal IOs (enabled by CFG_2[ODT_CFG]) and b) the external MODT[] signals going to the SDRAM? If yes, what is the delay between the assertion of the internal ODT signal (e.g. set by TIMING_CFG_5[RODT_ON])and actual switching of the internal RTT? These are related to the ODT timings to the DRAM. If ODT during reads is not used, then the RODT_ON and RODT_OFF values can be cleared. These are the ODT signal turn ON/OFF latency. For DDR3 it is defined as WL-2=CWL+AL-2. If one DIMM slot is used then there is no need for dynamic ODT setting.

Is it correct that TIMING_CFG_5[RODT_ON] and TIMING_CFG_5[RODT_OFF] do not affect internal ODT circuit for MPC8535? These values are always set in u-boot for our DDR3 based boards (e.g. P2020DS, MPC8569MDS). However external ODT is never enabled for SDRAM reads, this could lead to a conclusion that internal ODT is also affected by the TIMING_CFG_5 setting. Can you comment? TIMING_CFG_5 register is only for DRAM ODT (external ODT), this is verified and confirmed. As for your suggestion that because in most cases the read ODT on DRAM is off and hence it has something to do with internal ODT is not a valid assumption. The Read ODT for DRAM is an option available if required. In most cases it will not apply, but there may be a configuration that may require it and then the option is available for such users. Please clarify the meaning of TIMING_CFG_5 register for DDR3 controller of the MPC8535. The sentence ".. relevant ODT signal(s)" is common to all fields. What is this referring to? Is that both a) an internal signal controlling internal IOs (enabled by CFG_2[ODT_CFG]) and b) the external MODT[] signals going to the SDRAM? If yes, what is the delay between the assertion of the internal ODT signal (e.g. set by TIMING_CFG_5[RODT_ON])and actual switching of the internal RTT? These are related to the ODT timings to the DRAM. If ODT during reads is not used, then the RODT_ON and RODT_OFF values can be cleared. These are the ODT signal turn ON/OFF latency. For DDR3 it is defined as WL-2=CWL+AL-2. If one DIMM slot is used then there is no need for dynamic ODT setting.

For MPC8360, is any way that the CPU can read and write the full 72-bit wide DDR memory bus, bypassing the ECC logic? I want to know if the memory controller can be configured for the 72-bit wide DDR memory bus to bypass the ECC logic. It is not possible to bypass the ECC and read/write using full 72-bit wide bus. The controller uses the last byte lane to generate ECC info and cannot be bypassed. For MPC8360 DDR SDRAM refresh, can you please advise how to "exactly" calculate the appropriate value of [REFINT] if such worst case scenario in which refresh command issue timing is postponed is taken into account? The refresh interval should be set as high as allowable by the DRAM specifications. This should be calculated by using tREFI in the DRAM specifications, which may depend upon the operating temperature of the DRAM. In addition, to allow a memory transaction in progress to be completed when the refresh interval is reached and not violating the device refresh period, set the REFINT value to a value less than that calculated by using tREFI. The value selected for REFINT could be larger than tREFI if the DDR_SDRAM_CFG[NUM_PR] has a value higher than 1. To calculate the max possible value when DDR_SDRAM_CFG[NUM_PR] is higher than 1, use the following formula: (tREFI/clk period) x (NUM_PR) = REFINT A timing tDISKEW (skew between MDQS and MDQ) is depicted in DDR2 and DDR3 SDRAM Interface Input Timing Diagram in MPC8360 Hardware spec. For measuring tDISKEW, please instruct me from which point of the MDQS waveform and to which point of MDQ waveform should be measured? For measuring MDQS, it should be at the cross point. For case of MDQ it is derated to the VREF. Why does MCK to MDQS Skew tDDKHMH has such a high value of +/-525ps for DDR3 800M data rate for MPC8360? I am afraid that write-leveling can NOT remove all internal MCK to MDQS skew from tDDKHMH. Can you please let me know how much internal skew will be removed after write-leveling? tDDKHMH value of +/-525ps for MPC8360 part is a conservative value in the HW spec. For DDR3 with write leveling enabled, this AC timing parameter would be a non-factor.

Please specify the DDR read only and write only counters for MPC8308. Event 19 counts DDR reads only while event 27 counts DDR writes only in MPC8308. How are DDR errors cleared in the ESUMR reg (bit 8)? Do they need to re-init the DDR? You need to clear the ERR_DEFECT [MBE] bit (write 1 to clear). After that the ESUMR bit 8 will be cleared.