UJA1169ATK/F V1 undervoltage reset

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UJA1169ATK/F V1 undervoltage reset

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larry_he
Contributor I

Hello, we use battery to supply VBAT(6.66V~7V), V1RTSUC is 80% and V1RTC is 90%, then SBC will reset, and RSS in Main status register(03h) will return 10011(V1 undervoltage).

V1 undervoltage,VBAT is OKV1 undervoltage,VBAT is OK

Increase the voltage on VBAT to 8V, the temperature will influence V1: UJA1169 will be OK below 65℃;while it will reset due to V1 undervoltage above 65℃.

When VBAT is 13V, the SBC is OK.

So, why VBAT and temperature will result in V1 undervoltage?

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guoweisun
NXP TechSupport
NXP TechSupport

V1 is the internal LDO of UJA1169, so the MOSFET Rdson will increase when temperature rise.

So you can get the temperature affect the V1 of UJA1169.

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JLDN0101
Contributor I

HI.guoweisun

I would like to ask a technical question about the UJA1169A, and since I didn't find a way how to post a new thread, this is the only way I can ask you.

As shown in the figure below, Vth(sw)r is the threshold for the rising edge from a low level to a high level, and Vth(sw)f is the threshold for the falling edge from a high level to a low level, why is there an intersection between these two thresholds?2.8V is contained within 3.75VHow is this understood?

For the UJA1169A, can the WAKE pin be internally configured with a pull-up or pull-down circuit? If the input signal is active low, must the WAKE pin have a resistor pull-up circuit?

JLDN0101_0-1697188461125.png

 

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guoweisun
NXP TechSupport
NXP TechSupport

这个客户提交了一个ticket今天已经帮他回复了

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guoweisun
NXP TechSupport
NXP TechSupport

如果是其他的topic,我建议您直接提交ticket下面的链接需要您的邮箱注册,我们会一对一的提供支持,回复的内容只有您自己看得到:

Home (nxp.com)

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larry_he
Contributor I

But will 65℃ make undervoltage happen? And when VBAT is 13V, 65℃ will not result in V1 undervoltage.

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guoweisun
NXP TechSupport
NXP TechSupport

For the LDO,VOUT= Vin - Vdrop, Vdrop will be affected by the Rdson of internal MOSFET, when the VIN and VOUT are similar value, the UV condition will easily happen.

 

 

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1,256 Views
JLDN0101
Contributor I

HI.guoweisun

I would like to ask a technical question about the UJA1169A, and since I didn't find a way how to post a new thread, this is the only way I can ask you.

As shown in the figure below, Vth(sw)r is the threshold for the rising edge from a low level to a high level, and Vth(sw)f is the threshold for the falling edge from a high level to a low level, why is there an intersection between these two thresholds?2.8V is contained within 3.75VHow is this understood?

For the UJA1169A, can the WAKE pin be internally configured with a pull-up or pull-down circuit? If the input signal is active low, must the WAKE pin have a resistor pull-up circuit?

 

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1,587 Views
larry_he
Contributor I

Is Rdson RON(BAT-V1) (Can VBAT be 2.8V?)? Or do you have the value of Rdson?

2.png

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guoweisun
NXP TechSupport
NXP TechSupport

是这个参数,我从你抓的波形上看V1输出往下掉的很厉害,可能是瞬态电流太大导致的。

你可以问问客户他这个测试条件瞬态电流能到多少?是不是超出了规格?正常值带载能力也就是200mA左右!

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