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Contributor III

We are using the PF8200DB and PF8200ES in a new design and were looking for a signal to monitor to check that the PMICs had turned on successfully (closed loop boot process).

In the OTP reports for each chip, it lists PGOOD as being OFF and the level stays low in the sequencing diagram.
Am I correct in assuming this signal is disabled by default?
I can use the RESETMCU signal, but this goes high regardless of any OV/UV faults.



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NXP TechSupport
NXP TechSupport

Hi Peter,


Not necessarily, if PGOOD as being OFF and the level stays low in the sequencing diagram, it can announce that there is a fault with a regulator or that, as you assumed, this signal is disabled by default. However, you would need to know how is the PGOOD function configured to make sure what is happening.


PGOOD is a programable Open Drain Output as Power good indicator or GPO output.


When OTP_PG_ACTIVE = 0, the PGOOD pin is used as a general purpose output.

As a GPO, during the run state, the state of the pin is controlled by the RUN_PG_GPO bit in the functional I2C registers:

  • When RUN_PG_GPO = 1, the PGOOD pin is high
  • When RUN_PG_GPO = 0, the PGOOD pin is low

When used as a GPO, the PGOOD pin can be enabled high as part of the power up sequence as programmed by the OTP_SEQ_TBASE[1:0] and the OTP_PGOOD_SEQ[7:0] bits. If enabled as part of the power up sequence, both the RUN_PG_GPO and STBY_PG_GPO bits are loaded with 1, otherwise they are loaded with 0 upon power up.


When OTP_PG_ACTIVE = 1, the PGOOD pin is in Power good (PG) mode and it acts as a PGOOD indicator for the selected output voltages in the PF8100/PF8200.

There is an individual PG monitor for every regulator. Each monitor provide an internal PG signal that can be selected to control the status of the PGOOD pin upon an OV or UV condition when the corresponding SWxPG_EN / LDOxPG_EN bits are set. The status of the PGOOD pin is a logic AND function of the internal PG signals of the selected monitors.

  • When the PG_EN = 1, the corresponding regulator becomes part of the AND function that controls the PGOOD pin.
  • When the PG_EN = 0, the corresponding regulator does not control the status of the PGOOD pin.

The PGOOD pin is pulled low when any of the selected regulator outputs falls above or below the programmed OV/UV thresholds and a corresponding OV/UV interrupt is generated. If the faulty condition is removed, the corresponding OV_S/UV_S bit goes low to indicate the output is back in  regulation, however, the interrupt remains latched until it is cleared.


In the Off mode and during the power up sequence, the PGOOD pin is held low until RESETBMCU is ready to be released, at this point, the PG monitors are unmasked and the PGOOD pin is released high if all the internal PG monitors are in regulation.

In the event that one or more outputs are not in regulation by the time RESETBMCU is ready to de-assert, the PGOOD pin is held low and the PF8100/PF8200 performs the corresponding fault protection mechanism as described in Section 14.7.1 "Fault monitoring during power up state" of the datasheet.


Specifically answer to your question, on both, PF8200DB and PF8200ES, PGOOD is OFF by default, you can confirm this in the Power Up sequence summary on section 5 of the OTP program ID documents:




For both cases, RESETBMCU is turned on during the power up sequence slot #20, at the very end of the power up sequence, so this pin can be used as a power good indicator regardless of any OV/UV faults.

If one regulators fails during power up, RESETBMCU should not go HIGH.