What are the DMIPS/MHz and GFLOP number of P5010/ 20 processors ?

[doner_t]

Hello,

• I need to DMIPS/MHz and GFLOP number of e5500 core. Could you help me ?
• Another question is that does e5500 core provide ECC on its L1 cache ?

Best Regards,

Tugay

[ufedor · Accepted solution]

1) 3.0 DMIPS/MHz

2) ECC is not implemented.

The L1 caches have:

— Instruction cache: 1 parity bit per word of instruction, 1 bit of parity per tag

— Data cache: 1 parity bit per byte of data, 1 bit of parity per tag