P1010 SPI boot fails rarely

[tkato]

Hi,

We designed a board that implements the P1010 and manufactured several of them for evaluation.
One of the boards rarely fails to boot after power-on.

In order to make the board SPI bootable, I set the cfg_rom_loc[0:3] pin to 0110, input power and clock, and then released the reset.
When the power is turned on in this state, the SPI clock may not be output about once or twice in 100 times.

This phenomenon does not occur on all boards, but only on one specific board.
If there is no problem with the cfg_rom_loc[0:3] pins or the clock or reset, what are some other possible causes?

Best Regards

[ufedor · Accepted solution]

Please confirm that TRST_B is pulsed low (asserted) during POR - refer to the AN4534 - P1010 Design Checklist, Table 30. JTAG system-level checklist, Boundary-scan testing.

[tkato]

Hi ufedor

TRST_B is always input High.
I did an experiment by inputting a low pulse synchronized with HRESET_B to TRST_B.
The problem did not occur even after 500 times of power-on.
This is a surprising result, but it was very helpful. Thank you!

But why does it malfunction if I input something other than Low at POR?
Even if this non-Low level input is the cause, I don't understand why the problem occurs rarely, not always.

[ufedor]

> But why does it malfunction if I input something other than Low at POR?

Because in the P1010 Design Checklist, Table 30. JTAG system-level checklist, Boundary-scan testing it is written:

"Ensure that TRST is asserted during power-on reset flow to ensure that the JTAG boundary logic does not interfere with normal chip operation."

[tkato]

I found out that this problem does not happen 100% of the time, but in rare cases the boundary scan circuit interferes.
This was very helpful. Thank you very much.