JTAG access p1020 CCSRBAR memory

[zzzzzzz]

Hi all .

        i have a custom board of P1020 which i want read CCSRBAR value after the board power up by JTAG. The e500 core have only 4K tlb memory map valid after reset , the CCSRBAR 1M memory don't have default TLB to map it . I find no TLB correspond to CCSRBAR memory have been set up before JTAG access the memory region .  The AN3366 "Simplifying Board Bringup" pdf show how to set up Initialization file for JTAG ,  i can't find any step to create TLB before access CCSRBAR region.  Is there no need set TLB for CCSRBAR region ?  can someone give me some suggestion ?

thank you 

[ufedor · Accepted solution]

Please note that correctly configured TLB is always required when Core is accessing memory.

CodeWarrior (or another debugger) reads and writes target hardware memory through the SAP (System Access Port) which is independent of the Core complex (including MMU), so it is able to use direct physical addresses to perform its operations.

Right after reset it is possible to access 1 MB CCSRBAR and 4KB default boot ROM memory spaces by means of the SAP.