How to disable L2-cache on P1022DS

[perrub]

We are now utilizing our P1022 developent systems (P1022DS) for software component testing (unit/module testing).

We would like to extend these tests to include execution time measurements. The L2-cache is disabled in our target system, so in order to get comparable values we need to disable it for the Linux system running on the P1022DS as well. How do we proceed to achieve this?

(We use a proprietary OS for our target system, so - apparently - we lack the necessary expertise in Linux.)

[lunminliang]

I am afraid there is no option to do this except modify the source code.

[perrub]

I was hoping for a more convenient way, but I didn't really expect it...

From the reference manual: The L2 cache is disabled by setting L2 enable (L2E, bit 0) of the L2 Control Register (L2CTL) to 0. L2CTL is memory mapped at an offset of 0x20000 from the Configuration, Control, and Status Register Base Address.

• How do we find out which Base Address our system use?
• How do we actually access the L2CTL register? I suspect we need user privileges of some kind, and perhaps some kind of address processing (remapping)...?

[perrub]

We ended up writing a loadable kernel module, with the core part being these rows:

phys_addr_t L2CTL = get_immrbase() + 0x20000;

void* L2_controller = ioremap_nocache(L2CTL, 4);

iowrite8(0x50, L2_controller);

This seems to do the trick for us.