DDR3 connection between the clock and the CKE

取消
显示结果 
显示  仅  | 搜索替代 
您的意思是: 

DDR3 connection between the clock and the CKE

595 次查看
zeevg
Contributor I

Hi,

when working with DDR3 what are the connection between the clock and the CKE (clock enable)?

could I work with two clock signals and one CKE?

could I work with any CKE for any clock?

pls. advise.

Zeev Gerber

标签 (1)
0 项奖励
1 回复

406 次查看
ufedor
NXP Employee
NXP Employee

Please refer to the AN3940 - Hardware and Layout Design Considerations for DDR3 SDRAM, Table 1. DDR3 designer checklist:

  1. Connect each of the MODT signals that are in the same group to the same physical memory bank:
  • MODT(0), MCS(0), MCKE(0)
  • MODT(1), MCS(1), MCKE(1)
  • MODT(2), MCS(2), MCKE(2)
  • MODT(3), MCS(3), MCKE(3)
0 项奖励