Available docs on the performance of P2020RDB-PCA H/W time stamping for IEEE 1588 PTP?

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Available docs on the performance of P2020RDB-PCA H/W time stamping for IEEE 1588 PTP?

Contributor II


I have been working with P2020RDB-PCAs and QorIQ SDK 1.9 for highly precise clock synchronization because the platform supports the IEEE 1588 H/W (hardware) time stamping and physical pps. 

Recently, for a part of rigorous performance evaluations, I have attempted to analyze and estimate the performance of HW time stamping.

I would like to inquire where I can find the related documents on the performance.

If the docs are not opened to the public, I would like to know the statistics of the time stamping 'error' including the PDF (probabilistic density function) type, mean, variance (or standard deviation), and the layer (e.g. MAC, PHY) where the Tx/Rx time stampings are performed.

Could you please let me know where I can find such information?

Hope to get the help soon.

Please stay healthy.

Best regards.


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4 Replies

Contributor II

Hi, TechSupporter.

Thanks for the reply.

I had read and studied the application notes you mentioned. However, I could not found the information about 'hardware time stamping error'.

Especially, the note AN4326 handles TSEC_1588_CLK_IN, CLK_OUT, ALARM_OUT1, and ALARM_OUT2. The interfaces are used to test the precision of clock synchronization, as far as I understand.

I guess that your development teams measured the statistics of 'hardware time stamping error' when they evaluated the performance and validity.

Could you please provide the information?



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NXP TechSupport
NXP TechSupport

Please refer to the attached document.

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Contributor II

First of all, thank you for the document. 

However, the document does not include information I mentioned.

The document seems to provide a profiled IEEE 1588 synchronization error in an environment where the IEEE 1588 hardware timestamping was used and two nodes were directly linked without a networking device like switch.

Although the environment without a network device minimizes the error from link asymmetry, I think that it is not possible to estimate 'hardware timestamping error' from the result sheet because the 'hardware timestamping error' is compensated in the calculation process of the IEEE 1588 PTP.

For example, there are four hardware timestamping errors. Two Tx timestamping errors, err_tx1 and err_tx2, occur when the master and slave nodes transmit SYNC and DELAY-REQ messages and measure timestamps, respectively. Two Rx timestamping errors, err_rx1 and err_rx2, occur when they receive the messages and measure timestamps.

The range of err_tx1/2 and err_rx1/2 would be perhaps picoseconds level. Furthermore, according to the IEEE 1588 PTP, offset 'O' is basically calculated by O = {(t3 - t1) - (t4 - t2)}/2 where t1&t3 are Tx timestamps and t2&t4 are Rx timestamps in each nodes, so that they are compensated by each other in the calculation process. 

Please refer to the following papers written by R. Exel:
1) High Accurate Timestamping by Phase and Frequency Estimation, ISPCS, 2009
url: https://ieeexplore.ieee.org/document/5340223

2) Highly Accurate Timestamping for Ethernet-Based Clock Synchronization, Journal of Computer Networks  and Communications, 2012
url: https://www.hindawi.com/journals/jcnc/2012/152071/

The information I would like to ask is depicted in 1)-Fig.5 and 2)-Fig.8. 
(I guess, you have a right to access and download the documents.)

Appreciate for the result sheet, again.

However, the sheet is not enough, sadly.

Could you please help me to obtain information including numerical data and density like in 1)-Fig.5 and 2)-Fig.8?

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