can kw45 LPI2C work when the chip is deep sleep mode?

[jeff56]

The kw45 reference manual,  "Table 285. LPI2C low-power modes" says that:

Deep Sleep

Before entering Deep Sleep mode, the LPI2C waits for the current transfer to finish any pending operation, while temporarily ignoring MCR[DOZEN].

i don't understand what this means. 

i wanna know, after the chip enter Deep Sleep mode, can the LPI2C(such as slave mode) work normally , and wakeup the chip when receive data from master?

[EduardoZamora · Accepted solution]

Hello @jeff56

Hope you are doing well.

According to Section 28.3.3 Deep Sleep mode, peripherals inside VDD_CORE_WAKE subdomain can remain operational using an asynchronous clock and can wake the device.

Functionality will depend on the instance in use. LPI2C0 is optional in Deep Sleep mode (KW45 Reference Manual, Section 28.4 Module operation in low power modes, Table 207: Cortex M33 core module operation in low power modes) as it is inside VDD_CORE_WAKE subdomain (Table 205: Peripheral power domain assignment).

To try to enable this peripheral in Deep Sleep mode, Functional Clock Mux should be configured selecting a clock that is available/functional in Deep Sleep mode and a proper Clock Configuration should be selected in LPI2C0 Reset and Clock Control (MRCC_LPI2C0).

Regards,
Eduardo.