Updating DDR-PHY Firmware NOR Flash Address Location in Custom LX2160a Board

[saidivvela]

Hi,

I'm currently working on a custom board utilizing the LX2160a processor with an XSPI flash to store firmware and boot from it.
Looking into the NOR flash address location for the DDR-PHY firmware within the LSDK, I've noticed that it's set to 0x00800000. However, for our custom board's requirements, we need it to be at 0x00500000 instead.

Attaching the LSDK NOR-Flash Map.

I've attempted to locate this address within the Arm Trusted Firmware (ATF) repository, as BL2 handles the loading of this firmware, but I've been unable to find it.

Does anyone have information on how to update the DDR-PHY firmware NOR flash address location? I assume it must be somewhere within the ATF repository since BL2 loads this firmware.

Any guidance or pointers would be greatly appreciated.

Thank you,

[yipingwang]

In atf source code, please modify the following in plat/nxp/common/fip_handler/ddr_fip/ddr_io_storage.h.

#define PLAT_DDR_FIP_OFFSET 0x800000

[saidivvela]

Thank you for the response. 

I did try that before and I tried to do again when you suggested now. 

That MACRO is not having any impact on the location of DDR-PHY. 

I generated a pbl with the suggested change and then erased the DDR phy from default location 0x800000 and flashed the image at a custom location 0x8800000.

I see the below error. It is unable to find the PHY firmware to train.

INFO: pll_ctrl2 = 0x19
INFO: SOC_SI_REV = 2
INFO: dll_lck_param = 0x212
INFO: dll_gain_ctl = 0x61
INFO: prog_acx4_anib_dis 0x0
INFO: Initialize PHY 1 config
INFO: pll_ctrl2 = 0x19
INFO: SOC_SI_REV = 2
INFO: dll_lck_param = 0x212
INFO: dll_gain_ctl = 0x61
INFO: prog_acx4_anib_dis 0x0
INFO: Load 1D firmware
WARNING: Firmware Image Package header check failed.
WARNING: Failed to obtain reference to image id=36 (-2)
ERROR: Failed to load 36 firmware.
ERROR: Loading firmware failed (error code -2)
ERROR: Calculating DDR PHY registers failed.
INFO: Time before programming controller 401 ms
INFO: Program controller registers
INFO: Disable address decoding
INFO: PHY handshake completed, timer remains 40
INFO: total size 16 GB
INFO: Need to wait up to 2840 ms
ERROR: Found training error(s): 0x100
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
ERROR: Asserting as the DDR is not initialized yet.ASSERT: plat/nxp/common/setup/ls_bl2_el3_setup.c:285
BACKTRACE: START: assert
0: EL3: 0x18017240
1: EL3: 0x1801a668
2: EL3: 0x18015a84
3: EL3: 0x1800da6c
4: EL3: 0x1800d108
BACKTRACE: END: assert

[yipingwang · Accepted solution]

It seems that the offset 0x8800000 exceeds the size of XSPI NOR flash.

[saidivvela]

Our custom board has 256 MB of flash so I was using this address.
I used 0x500000 address location and it works fine. Thank you.
Not sure if atf doesn't support flash after 64MB.