T1042 DDR controller has no MCK output

[jingyibin]

I have a T1042 board design with DDR3L, the board can be correctly run in L2 cache. The core clk and the platform clk are both correct. However, the DDR controller has no DDRCLK output, and the MCKE always be low. Is there any way to locate the problem and fix the issue? Thanks

[Bulat]

DDR MCK outputs become active as soon as the user enables at least one DDR's CS, i.e. DDR_CSn_CONFIG[CS_EN]=1.

Regards,

Bulat

[jingyibin]

I tried to enable CS_EN and MEM_EN, but there is still no MCK. Actually, I used JTAG in hardcoded RCW option for the test, is it possible that the DDR controller would not output MCK in hardcoded RCW option?

[Bulat]

Hardcoded RCW is ok for SDRAM, however RCW itself is not enough for MCK clock. As I wrote you need to enable at least one DDR's CS.

Regards,

Bulat