PTN5150 for USB Type-C

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PTN5150 for USB Type-C

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ydr_vici
Contributor I

Hi,

I was reviewing the datasheet for PTN5150. I am interested in upgrading a USB Type A solution to USB Type-C. What is the difference between versions of PTN5150? Is there a development kit to speed up the test process? Thanks.

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ydr_vici
Contributor I

Ok, got it. Thank you!

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reyes
NXP TechSupport
NXP TechSupport

Hi,

There are 3 different part numbers related to the PTN5150 CC logic for USB Type-C applications and the difference between these 3 versions of the device is only the functionality of the Pin 11:

  1. PTN5150AHX

Pin 11 = EXT_SEL

Use Case: EXT_SEL directly controls PTN36043 or CBTL02043. Save one GPIO pin from PMIC to USB 3.0 Switch.

 

  1. PTN5150HX

Pin 11 = ENB Active low

Use Case: Pin-to-pin compatible with competitors. When PMIC use active low to enable CC logic chip.

 

  1. PTN5150HHX

Pin 11 = EN Active High

Use Case: Pin-to-pin compatible with competitors. When PMIC use active high to enable CC logic chip.

 

Unfortunately there is no available development kit for the moment.


Have a great day,
Jose

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anton_curaj
Contributor I

Dear Jose,

I have read your response above and would like to ask additional questions.

We have selected the PTN5150HX version with Pin 11 = ENB Active Low, but the PTN5150HHX with Pin 11 = EN Active High would be equally suitable as well if this is the only difference.

However, datasheets of both parts on page 4 differ in another (important?) detail related to connection of the VBUS_DET pin to VBUS line.

- PTN5150HX (and also PTN5150AHX) recommends (prescribes?): "Directly tie to VBUS of the USB Type-C receptacle.".

- PTN5150HHX on the other side recommends (prescribes?): "One 1 MOhm +/-1 % external resistor required between system Vbus and VBUS_DET pin.".

1. VBUS_DET pin has 28V max tolerance in both cases, so why is the 1M series resistor required for one version but not for other two versions? 

2. These are actually two different conditions for (almost?) the same silicon. Could you please confirm there is a real internal difference on the VBUS_DET pin for different chip versions and explain its behaviour in both cases?

3. What is the internal structure of this pin for different chip versions (impedance, leakage, threshold, hysteresis,...) please?

4. We would like to operate PTN5150xHX in DRP and non-I2C mode.   

What is the internal timing / switching between DFP and UFP modes, detection of VBUS_DET and CCx pins status (voltage level). 

5. Could you please provide state (and timing) diagram and transition between subsequent connection events?

Is status of the ID and CON_DET pins based purely on static voltage levels on the CCx and VBUS_DET pins, or is there some dependency (state machine) on a previous connection state? Could you please provide deeper application details that are not covered in datasheet?

Looking forward to your support in advance.

Kind greetings,

Anton

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