MC56F84786 Continous Clock during data receive on SPI

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MC56F84786 Continous Clock during data receive on SPI

1,458件の閲覧回数
20Sidar04
Contributor III

Dear Mr. and Mrs., 

When i check results on Logic analyzer, SPI clock of MC56F84786 is not continous. I have attached results on message. When i worked with other brands microcontrollers, they have tranmit and receive functionality in one function. But When I checked Codewarriors IDE, it doesn’t Show any kind of function on Auto generated method section. Due to this reason, i implemented function like that by using seperate transmit and receive functions. As following PDF i send 0x92 and 3 byte 0x00. After sending each byte, I try to read response on SPI by using readbyte function. But during reading data, clock is not continous. When i check NXP community, some of microcontrollers family has continous clock for SPI. Is there solution for continous clock of MC56F84786. Thanks in advance for your precious supports. 

Regards.

Sidar.

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

The SPI timing is correct, based on SPI protocol, the SCK pin clock is NOT continuous.  In detail, when the /CS is high, this is not data transfer process, the SCK clock disappears, when the /CS is low, this is the data transfer process, the SCK clock appears.

Hope it can help you

BR

XiangJun Rong

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1,438件の閲覧回数
20Sidar04
Contributor III

For example, In the following SPI diagram, clock is continous during all the data transfer. 

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xiangjun_rong
NXP TechSupport
NXP TechSupport

Hi,

The SPI of MC56F847xx is called queued spi instead of quad spi, the quadSPI interface can communicate with quad flash, but the queued spi of MC56F847xx is a normal spi, it has different timing from that of quad spi.

Hope it can help you

BR

Xiangjun Rong

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1,427件の閲覧回数
20Sidar04
Contributor III
But as following picture show SPI with CS,CLK, DATA input and Data output. In addition, I use normal SPI interface of Flash not Quad SPI interface.
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1,440件の閲覧回数
20Sidar04
Contributor III

I mentioned about continous clock during Chip select low. 

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