LS1046A custom board: BL2: Failed to load image

[kkk_david]

I'm trying to bring up custom LS1046A board, but it fails due to memory initialization failure.

TFA version: 1.5
NXP LLDP L6.1.55_2.2.0

Board stuck at BL2. Here is the verbose output:

```

INFO: RCW BOOT SRC is IFC NOR
INFO: platform clock 700000000
INFO: DDR PLL1 1600000000
INFO: DDR PLL2 0
INFO: Time before programming controller 0 ms
INFO: Program controller registers
WARNING: Warning: Optimal CPO value not set.
INFO: total size 8 GB
INFO: Need to wait up to 2680 ms
INFO: Reading debug[9] as 0x10101010
INFO: Reading debug[10] as 0x10101010
INFO: Reading debug[11] as 0x10101010
INFO: Reading debug[12] as 0x10101010
INFO: cpo_min 0x10
INFO: cpo_max 0x10
INFO: debug[28] 0x70006f
WARNING: Warning: A009942 requires setting cpo_sample to 0x37
INFO: *0x1080000 = 0x1ff
INFO: *0x1080008 = 0x200023f
INFO: *0x1080010 = 0x240027f
INFO: *0x1080018 = 0x28002bf
INFO: *0x1080080 = 0x80010512
INFO: *0x1080084 = 0x202
INFO: *0x1080088 = 0x202
INFO: *0x108008c = 0x202
INFO: *0x1080100 = 0x21d1100
INFO: *0x1080104 = 0xff770010
INFO: *0x1080108 = 0xf8fc1265
INFO: *0x108010c = 0x5951a0
INFO: *0x1080110 = 0xc5208000
INFO: *0x1080114 = 0x401060
INFO: *0x1080118 = 0x1010631
INFO: *0x108011c = 0x100000
INFO: *0x1080120 = 0x600081f
INFO: *0x1080124 = 0x1ffe07ff
INFO: *0x1080130 = 0x2800000
INFO: *0x1080160 = 0x22d502
INFO: *0x1080164 = 0x6401400
INFO: *0x108016c = 0x25540000
INFO: *0x1080170 = 0x8a090705
INFO: *0x1080174 = 0xc6750605
INFO: *0x1080190 = 0x5060607
INFO: *0x1080194 = 0x7080804
INFO: *0x1080220 = 0x701
INFO: *0x1080224 = 0x8800000
INFO: *0x1080250 = 0x5447a00
INFO: *0x1080270 = 0xffff
INFO: *0x1080280 = 0xffffffff
INFO: *0x1080284 = 0xffffff7d
INFO: *0x1080288 = 0xffffffff
INFO: *0x108028c = 0xffffff7d
INFO: *0x1080290 = 0x1
INFO: *0x10802a0 = 0x1
INFO: *0x1080400 = 0x1692672c
INFO: *0x1080404 = 0x8c99d5a0
INFO: *0x1080408 = 0xe50eb14
INFO: *0x108040c = 0xc8000000
INFO: *0x1080b20 = 0x8080
INFO: *0x1080b24 = 0x80000000
INFO: *0x1080b28 = 0x80040000
INFO: *0x1080b2c = 0x80
INFO: *0x1080bf8 = 0x20502
INFO: *0x1080bfc = 0x100
INFO: *0x1080e40 = 0x80
INFO: *0x1080f04 = 0x3002
INFO: *0x1080f08 = 0xd
INFO: *0x1080f0c = 0x14000c20
INFO: *0x1080f24 = 0x10101010
INFO: *0x1080f28 = 0x10101010
INFO: *0x1080f2c = 0x10101010
INFO: *0x1080f30 = 0x10101010
INFO: *0x1080f34 = 0x10103000
INFO: *0x1080f48 = 0x1
INFO: *0x1080f4c = 0x94000000
INFO: *0x1080f50 = 0x10001000
INFO: *0x1080f54 = 0xf000f00
INFO: *0x1080f58 = 0xd000d00
INFO: *0x1080f5c = 0xc000c00
INFO: *0x1080f60 = 0x8000000
INFO: *0x1080f64 = 0x9000
INFO: *0x1080f68 = 0x20
INFO: *0x1080f70 = 0INFO: RCW BOOT SRC is IFC NOR
VERBOSE: Generic delay timer configured with mult=1 and div=25
INFO: RCW BOOT SRC is IFC NOR
INFO: platform clock 700000000
INFO: DDR PLL1 1600000000
INFO: DDR PLL2 0
INFO: Time before programming controller 0 ms
INFO: Program controller registers
WARNING: Warning: Optimal CPO value not set.
INFO: total size 8 GB
INFO: Need to wait up to 2680 ms
INFO: Reading debug[9] as 0x10101010
INFO: Reading debug[10] as 0x10101010
INFO: Reading debug[11] as 0x10101010
INFO: Reading debug[12] as 0x10101010
INFO: cpo_min 0x10
INFO: cpo_max 0x10
INFO: debug[28] 0x70006f
WARNING: Warning: A009942 requires setting cpo_sample to 0x37
INFO: *0x1080000 = 0x1ff
INFO: *0x1080008 = 0x200023f
INFO: *0x1080010 = 0x240027f
INFO: *0x1080018 = 0x28002bf
INFO: *0x1080080 = 0x80010512
INFO: *0x1080084 = 0x202
INFO: *0x1080088 = 0x202
INFO: *0x108008c = 0x202
INFO: *0x1080100 = 0x21d1100
INFO: *0x1080104 = 0xff770010
INFO: *0x1080108 = 0xf8fc1265
INFO: *0x108010c = 0x5951a0
INFO: *0x1080110 = 0xc5208000
INFO: *0x1080114 = 0x401060
INFO: *0x1080118 = 0x1010631
INFO: *0x108011c = 0x100000
INFO: *0x1080120 = 0x600081f
INFO: *0x1080124 = 0x1ffe07ff
INFO: *0x1080130 = 0x2800000
INFO: *0x1080160 = 0x22d502
INFO: *0x1080164 = 0x6401400
INFO: *0x108016c = 0x25540000
INFO: *0x1080170 = 0x8a090705
INFO: *0x1080174 = 0xc6750605
INFO: *0x1080190 = 0x5060607
INFO: *0x1080194 = 0x7080804
INFO: *0x1080220 = 0x701
INFO: *0x1080224 = 0x8800000
INFO: *0x1080250 = 0x5447a00
INFO: *0x1080270 = 0xffff
INFO: *0x1080280 = 0xffffffff
INFO: *0x1080284 = 0xffffff7d
INFO: *0x1080288 = 0xffffffff
INFO: *0x108028c = 0xffffff7d
INFO: *0x1080290 = 0x1
INFO: *0x10802a0 = 0x1
INFO: *0x1080400 = 0x1692672c
INFO: *0x1080404 = 0x8c99d5a0
INFO: *0x1080408 = 0xe50eb14
INFO: *0x108040c = 0xc8000000
INFO: *0x1080b20 = 0x8080
INFO: *0x1080b24 = 0x80000000
INFO: *0x1080b28 = 0x80040000
INFO: *0x1080b2c = 0x80
INFO: *0x1080bf8 = 0x20502
INFO: *0x1080bfc = 0x100
INFO: *0x1080e40 = 0x80
INFO: *0x1080f04 = 0x3002
INFO: *0x1080f08 = 0xd
INFO: *0x1080f0c = 0x14000c20
INFO: *0x1080f24 = 0x10101010
INFO: *0x1080f28 = 0x10101010
INFO: *0x1080f2c = 0x10101010
INFO: *0x1080f30 = 0x10101010
INFO: *0x1080f34 = 0x10103000
INFO: *0x1080f48 = 0x1
INFO: *0x1080f4c = 0x94000000
INFO: *0x1080f50 = 0x10001000
INFO: *0x1080f54 = 0xf000f00
INFO: *0x1080f58 = 0xd000d00
INFO: *0x1080f5c = 0xc000c00
INFO: *0x1080f60 = 0x8000000
INFO: *0x1080f64 = 0x9000
INFO: *0x1080f68 = 0x20
INFO: *0x1080f70 = 0x70006f
INFO: *0x1080f94 = 0x80000000
INFO: *0x1080fb0 = 0x3
INFO: *0x1080fb4 = 0x1f1f1f1f
INFO: *0x1080fb8 = 0x1f1f1f1f
INFO: *0x1080fbc = 0x1f1f1f1f
INFO: *0x1080fc0 = 0x1f1f1f1f
INFO: *0x1080fc4 = 0x1f1f1f1f
INFO: *0x1080fc8 = 0x1f1f1f1f
INFO: *0x1080fcc = 0x1f1f1f1f
INFO: *0x1080fd0 = 0x1f1f1f1f
INFO: *0x1080fd4 = 0x1f1f1f1f
INFO: *0x1080fd8 = 0x1f1f1f1f
INFO: *0x1080fdc = 0x1f1f1f1f
INFO: *0x1080fe0 = 0x1f1f1f1f
INFO: *0x1080fe4 = 0x1f1f1f1f
INFO: *0x1080fe8 = 0x1f1f1f1f
INFO: *0x1080fec = 0x1f1f1f1f
INFO: *0x1080ff0 = 0x1f1f1f1f
INFO: *0x1080ff4 = 0x1f1f1f1f
INFO: *0x1080ff8 = 0x1f1f1f1f
INFO: *0x1080ffc = 0x1f003f38

NOTICE: 8 GB DDR4, 64-bit, CL=15, ECC off
INFO: Time used by DDR driver 1371 ms
VERBOSE: Memory seen by this BL image: 0x10000000 - 0x10013000
VERBOSE: Code region: 0x10000000 - 0x10008000
VERBOSE: Read-only data region: 0x10008000 - 0x1000b000
VERBOSE: DRAM Region 0: 0x80000000 - 0xfbdfffff
VERBOSE: Secure DRAM Region 0: 0xfbe00000 - 0xffffffff
mmap:
VA:0x1000000 PA:0x1000000 size:0xf000000 attr:0x8 granularity:0x40000000
VA:0x10000000 PA:0x10000000 size:0x8000 attr:0x2 granularity:0x40000000
VA:0x10008000 PA:0x10008000 size:0x3000 attr:0x22 granularity:0x40000000
VA:0x10000000 PA:0x10000000 size:0x13000 attr:0xa granularity:0x40000000
VA:0x60000000 PA:0x60000000 size:0x8000000 attr:0xa granularity:0x40000000
VA:0x80000000 PA:0x80000000 size:0x7be00000 attr:0x1a granularity:0x40000000
VA:0xfbe00000 PA:0xfbe00000 size:0x4200000 attr:0xa granularity:0x40000000

VERBOSE: Translation tables state:
VERBOSE: Xlat regime: EL3
VERBOSE: Max allowed PA: 0xffffffffff
VERBOSE: Max allowed VA: 0xffffffffff
VERBOSE: Max mapped PA: 0xffffffff
VERBOSE: Max mapped VA: 0xffffffff
VERBOSE: Initial lookup level: 0
VERBOSE: Entries @initial lookup level: 2
...
NOTICE: BL2: v1.5(debug):
NOTICE: BL2: Built : 07:13:31, Jun 6 2024
INFO: Configuring TrustZone Controller
VERBOSE: TrustZone : Configuring region 0 (TZC Interface Base=0x1500000 sec_attr=0x0, ns_devs=0x0)
INFO: Value of region base = ffe00000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 1)...
VERBOSE: TrustZone : ... base = fbe00000, top = ffdfffff,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0x0)
INFO: Value of region base = 1ffe00000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 2)...
VERBOSE: TrustZone : ... base = ffe00000, top = ffffffff,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff)
INFO: Value of region base = fbe00000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 3)...
VERBOSE: TrustZone : ... base = 80000000, top = fbdfffff,
VERBOSE: TrustZone : ... sec_attr = 0x3, ns_devs = 0xffffffff)
INFO: Value of region base = a80000000
VERBOSE: TrustZone : Configuring region (TZC Interface Base: 0x1500000, region_no = 4)...
VERBOSE: TrustZone : ... base = 880000000, top = 9ffffffff,
VERBOSE: TrustZone : ... sec_attr = 0x0, ns_devs = 0xffffffff)
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
WARNING: Firmware Image Package header check failed.
VERBOSE: Trying FUSE IO
WARNING: Failed to obtain reference to image id=3 (-2)
ERROR: BL2: Failed to load image (-2)
Authentication failure

```

On the QCVS tool 'Centering the clock'  test failed. I got the following log.
```

#################### Result for: wrlvl_searcher ###### Run 1 ######################################

Test result: [
============================================================
Updated: WRLVL_CNTL = 0x86750605, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750607, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750609, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x8675060B, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x8675060D, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x8675060F, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750611, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750613, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750615, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750617, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x86750619, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Incrementing WRLVL_START...
============================================================
Updated: WRLVL_CNTL = 0x8675061B, WRLVL_CNTL_2 = 0x00000000, WRLVL_CNTL_3 = 0x00000000, SDRAM_CLK_CNTL = 0x02800000

Validation cannot proceed due to other DDR hardware or software issues!
Common hardware issues include:
- DRAM reset is not implemented correctly
- Voltages are not present
- Signals not connected correctly
- Differential signals connected in wrong polarity
Common software issues include:
- wrong DDR frequency selected
- wrong DDR configuration selected
- incorrect SPD data
- DDR4 DQn_MAP configured values are incorrect
<<Test failed!>>
{{Validation cannot proceed due to other DDR hardware or software issues!}}

Err. capture registers:
0xE20, 0x00000000 0xE24, 0x00000000 0xE28, 0x00000000 0xE40, 0x00000080
0xE44, 0x00000100 0xE48, 0x00000000 0xE4C, 0x00000000 0xE50, 0x00000000
0xE54, 0x00000000 0xE58, 0x00010000

Dump:
0xF00, 0x00000000 0xF04, 0x00003002 0xF08, 0x0000000D 0xF0C, 0x14000C20
0xF10, 0x00000000 0xF14, 0x00000000 0xF18, 0x00000000 0xF1C, 0x00000000
0xF20, 0x00000000 0xF24, 0x10101010 0xF28, 0x10101010 0xF2C, 0x10101010
0xF30, 0x10101010 0xF34, 0x10103000 0xF38, 0x00000000 0xF3C, 0x00000000
0xF40, 0x00000000 0xF44, 0x00000000 0xF48, 0x00000001 0xF4C, 0x94000000
0xF50, 0x30003000 0xF54, 0x2F002F00 0xF58, 0x3D003D00 0xF5C, 0x3C003C00
0xF60, 0x36000000 0xF64, 0x00009000 0xF68, 0x00000020 0xF6C, 0x00000000
0xF70, 0x0070006F 0xF74, 0x00000000 0xF78, 0x00000000 0xF7C, 0x00000000
0xF80, 0x00000000 0xF84, 0x00000000 0xF88, 0x00000000 0xF8C, 0x00000000
0xF90, 0x00000000 0xF94, 0x80000000 0xF98, 0x00000000 0xF9C, 0x00000000
0xFA0, 0x00000000 0xFA4, 0x00000000 0xFA8, 0x00000000 0xFAC, 0x00000000
0xFB0, 0x00000003 0xFB4, 0x1F1F1F1F 0xFB8, 0x1F1F1F1F 0xFBC, 0x1F1F1F1F
0xFC0, 0x1F1F1F1F 0xFC4, 0x1F1F1F1F 0xFC8, 0x1F1F1F1F 0xFCC, 0x1F1F1F1F
0xFD0, 0x1F1F1F1F 0xFD4, 0x1F1F1F1F 0xFD8, 0x1F1F1F1F 0xFDC, 0x1F1F1F1F
0xFE0, 0x1F1F1F1F 0xFE4, 0x1F1F1F1F 0xFE8, 0x1F1F1F1F 0xFEC, 0x1F1F1F1F
0xFF0, 0x1F1F1F1F 0xFF4, 0x1F1F1F1F 0xFF8, 0x1F1F1F1F 0xFFC, 0x1F003F38

Data:
0x00000005 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
```
I tried to adjust Clock control and WL but it failed and threw same error after memory validation on QCVS tool. The following are the parameters for DDR. (TFA version is 1.5 as recommended by NXP for the boards with LS1046A)

```
const struct ddr_cfg_regs static_1600 = {
.cs[0].bnds = 0x01FF,
.cs[1].bnds = 0x0200023F,
.cs[0].config = 0x80010512,
.cs[1].config = 0x0202,
.cs[2].bnds = 0x0240027F,
.cs[3].bnds = 0x028002BF,
.cs[2].config = 0x0202,
.cs[3].config = 0x0202,
.cs[0].config_2 = 0x00,
.cs[1].config_2 = 0x00,
.cs[2].config_2 = 0x00,
.cs[3].config_2 = 0x00,
.sdram_cfg[0] = 0x45200000,
.sdram_cfg[1] = 0x00401070,
.timing_cfg[0] = 0x80770010,
.timing_cfg[1] = 0xB8BC02D5,
.timing_cfg[2] = 0x005951A5,
.timing_cfg[3] = 0x02111100,
.timing_cfg[4] = 0x00220002,
.timing_cfg[5] = 0x06401400,
.timing_cfg[7] = 0x25540000,
.timing_cfg[8] = 0x05447A00,
.dq_map[0] = 0x1692672C,
.dq_map[1] = 0x8C99D5A0,
.dq_map[2] = 0x0E50EB14,
.dq_map[3] = 0xC8000000,
.sdram_mode[0] = 0x01010631,
.sdram_mode[1] = 0x00100000,
.sdram_mode[2] = 0x00,
.sdram_mode[3] = 0x00,
.sdram_mode[4] = 0x00,
.sdram_mode[5] = 0x00,
.sdram_mode[6] = 0x00,
.sdram_mode[7] = 0x00,
.sdram_mode[8] = 0x0701,
.sdram_mode[9] = 0x08800000,
.sdram_mode[10] = 0x00,
.sdram_mode[11] = 0x00,
.sdram_mode[12] = 0x00,
.sdram_mode[13] = 0x00,
.sdram_mode[14] = 0x00,
.sdram_mode[15] = 0x00,
.md_cntl = 0x00,
.interval = 0x1FFE07FF,
.data_init = 0xDEADBEEF,
.clk_cntl = 0x02800000,
.init_addr = 0x00,
.ddr_sr_cntr = 0x0,
.init_ext_addr = 0x00,
.zq_cntl = 0x8A090905,
.wrlvl_cntl[0] = 0x86750609,
.wrlvl_cntl[1] = 0x09060603,
.wrlvl_cntl[2] = 0x030D0D00,
.cdr[0] = 0x800C0000,
.cdr[1] = 0x81,
};
```

[kkk_david]

There is no SPD on my target board. I did as you said. I have configured DDR according to the data sheet but it is failing again.

Here is my DDR registers configuration:

const struct ddr_cfg_regs static_2100 = {
.cs[0].bnds = 0x01FF,
.cs[1].bnds = 0x0200023F,
.cs[0].config = 0x80010512,
.cs[1].config = 0x0202,
.cs[0].config_2 = 0x00,
.cs[1].config_2 = 0x00,
.cs[2].bnds = 0x0240027F,
.cs[3].bnds = 0x028002BF,
.cs[2].config = 0x0202,
.cs[3].config = 0x0202,
.cs[2].config_2 = 0x00,
.cs[3].config_2 = 0x00,
.timing_cfg[0] = 0xFF770010,
.timing_cfg[1] = 0xF8FC1265,
.timing_cfg[2] = 0x005951A0,
.timing_cfg[3] = 0x021D1100,
.timing_cfg[4] = 0x0022D502,
.timing_cfg[5] = 0x06401400,
.timing_cfg[6] = 0x00000000,
.timing_cfg[7] = 0x25540000,
.timing_cfg[8] = 0x05447A00,
.timing_cfg[9] = 0x00000000,
.sdram_cfg[0] = 0x45208000,
.sdram_cfg[1] = 0x00401060,
.sdram_cfg[2] = 0x00,
.dq_map[0] = 0x1692672C,
.dq_map[1] = 0x8C99D588,
.dq_map[2] = 0x0E50C594,
.dq_map[3] = 0x48000000,
.sdram_mode[0] = 0x01010631,
.sdram_mode[1] = 0x00100000,
.sdram_mode[2] = 0x00,
.sdram_mode[3] = 0x00,
.sdram_mode[4] = 0x00,
.sdram_mode[5] = 0x00,
.sdram_mode[6] = 0x00,
.sdram_mode[7] = 0x00,
.sdram_mode[8] = 0x0701,
.sdram_mode[9] = 0x08800000,
.sdram_mode[10] = 0x00,
.sdram_mode[11] = 0x00,
.sdram_mode[12] = 0x00,
.sdram_mode[13] = 0x00,
.sdram_mode[14] = 0x00,
.sdram_mode[15] = 0x00,
.md_cntl = 0x00,
.interval = 0x1FFE07FF,
.data_init = 0xDEADBEEF,
.clk_cntl = 0x02400000,
.init_addr = 0x00,
.ddr_sr_cntr = 0x0,
.init_ext_addr = 0x00,
.zq_cntl = 0x8A090705,
.wrlvl_cntl[0] = 0x86750605,
.wrlvl_cntl[1] = 0x05060607,
.wrlvl_cntl[2] = 0x07080804,
.sdram_rcw[0] = 0x00,
.sdram_rcw[1] = 0x00,
.sdram_rcw[2] = 0x00,
.sdram_rcw[3] = 0x00,
.sdram_rcw[4] = 0x00,
.sdram_rcw[5] = 0x00,
.cdr[0] = 0x80080000,
.cdr[1] = 0x80,
.err_disable = 0x00,
.err_int_en = 0x00,
};

When DRAM data initialization ( D_INIT bit is set to 1)  i get the following output:

INFO: RCW BOOT SRC is IFC NOR
INFO: RCW BOOT SRC is IFC NOR
INFO: platform clock 700000000
INFO: DDR PLL1 1600000000
INFO: DDR PLL2 0
INFO: Time before programming controller 0 ms
INFO: Program controller registers
WARNING: Warning: Optimal CPO value not set.
INFO: total size 8 GB
INFO: Need to wait up to 2680 ms
ERROR: Found training error(s): 0x3000
ERROR: Error: Waiting for D_INIT timeout.
ERROR: Writing DDR register(s) failed
ERROR: Programing DDRC error
ERROR: DDR init failed.
NOTICE: Incorrect DRAM0 size is defined in platfor_def.h
ERROR: mmap_add_region_check() failed. error -22
ASSERT: lib/xlat_tables_v2/xlat_tables_internal.c:753

When DRAM data initialization ( D_INIT bit is set to 0):

INFO: RCW BOOT SRC is IFC NOR
INFO: RCW BOOT SRC is IFC NOR
INFO: platform clock 700000000
INFO: DDR PLL1 1600000000
INFO: DDR PLL2 0
INFO: Time before programming controller 0 ms
INFO: Program controller registers
WARNING: Warning: Optimal CPO value not set.
INFO: Reading debug[9] as 0x10101010
INFO: Reading debug[10] as 0x10101010
INFO: Reading debug[11] as 0x10101010
INFO: Reading debug[12] as 0x10101010
INFO: cpo_min 0x10
INFO: cpo_max 0x10
INFO: debug[28] 0x70006f
WARNING: Warning: A009942 requires setting cpo_sample to 0x37
INFO: *0x1080000 = 0x1ff
INFO: *0x1080008 = 0x200023f
INFO: *0x1080010 = 0x240027f
INFO: *0x1080018 = 0x28002bf
INFO: *0x1080080 = 0x80010512
INFO: *0x1080084 = 0x202
INFO: *0x1080088 = 0x202
INFO: *0x108008c = 0x202
INFO: *0x1080100 = 0x21d1100
INFO: *0x1080104 = 0xff770010
INFO: *0x1080108 = 0xf8fc1265
INFO: *0x108010c = 0x5951a0
INFO: *0x1080110 = 0xc5208000
INFO: *0x1080114 = 0x401060
INFO: *0x1080118 = 0x1010631
INFO: *0x108011c = 0x100000
INFO: *0x1080120 = 0x1000
INFO: *0x1080124 = 0x1ffe07ff
INFO: *0x1080128 = 0xdeadbeef
INFO: *0x1080130 = 0x2400000
INFO: *0x1080160 = 0x22d502
INFO: *0x1080164 = 0x6401400
INFO: *0x108016c = 0x25540000
INFO: *0x1080170 = 0x8a090705
INFO: *0x1080174 = 0xc6750605
INFO: *0x1080190 = 0x5060607
INFO: *0x1080194 = 0x7080804
INFO: *0x1080220 = 0x701
INFO: *0x1080224 = 0x8800000
INFO: *0x1080250 = 0x5447a00
INFO: *0x1080270 = 0x80000000
INFO: *0x1080280 = 0x444844
INFO: *0x1080284 = 0x1488f482
INFO: *0x1080288 = 0xffffffff
INFO: *0x108028c = 0xffff73ff
INFO: *0x1080290 = 0x1
INFO: *0x1080400 = 0x1692672c
INFO: *0x1080404 = 0x8c99d588
INFO: *0x1080408 = 0xe50c594
INFO: *0x108040c = 0x48000000
INFO: *0x1080b20 = 0x8080
INFO: *0x1080b24 = 0x80000000
INFO: *0x1080b28 = 0x80080000
INFO: *0x1080b2c = 0x80
INFO: *0x1080bf8 = 0x20502
INFO: *0x1080bfc = 0x100
INFO: *0x1080e40 = 0x80
INFO: *0x1080f04 = 0x2000
INFO: *0x1080f08 = 0xd
INFO: *0x1080f0c = 0x14000c20
INFO: *0x1080f24 = 0x10101010
INFO: *0x1080f28 = 0x10101010
INFO: *0x1080f2c = 0x10101010
INFO: *0x1080f30 = 0x10101010
INFO: *0x1080f34 = 0x10104000
INFO: *0x1080f48 = 0x1
INFO: *0x1080f4c = 0x11000000
INFO: *0x1080f50 = 0xf000f00
INFO: *0x1080f54 = 0xf000e00
INFO: *0x1080f58 = 0xc000c00
INFO: *0x1080f5c = 0xb000b00
INFO: *0x1080f60 = 0x8000000
INFO: *0x1080f64 = 0x9000
INFO: *0x1080f68 = 0x20
INFO: *0x1080f70 = 0x70006f
INFO: *0x1080f94 = 0x80000000

NOTICE: 8 GB DDR4, 64-bit, CL=15, ECC off
INFO: Time used by DDR driver 1029 ms
NOTICE: BL2: v1.5(debug):
NOTICE: BL2: Built : 07:08:39, Jul 1 2024
INFO: Configuring TrustZone Controller
INFO: Value of region base = ffe00000
INFO: Value of region base = 1ffe00000
INFO: Value of region base = fbe00000
INFO: Value of region base = a80000000
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
WARNING: Firmware Image Package header check failed.
WARNING: Failed to obtain reference to image id=3 (-2)
ERROR: BL2: Failed to load image (-2)
Authentication failure

[yipingwang · Accepted solution]

In QCVS DDR tool, if there is SPD on your target board, please create a QCVS DDR project with "reading from SPD" method, then do validation.

If no SPD, please fill the "Properties" panel according to your DDR datasheet, then start validation.

After all the validation in DDRv tool passing, please generate files used in atf.