How to set A/D sampling rate in CW for 56F8300E

[RSF]

I thought that if I set the conversion time in the A/D Bean and ran continuous conversions using start and stop and storing the data using GET16 in the ON_END event module my sampling rate would be the conversion time (eg conversion time of 4.533 us would yield a 220.6 kHz sampling rate) I tried this but the sampling rate seems considerably lower. Do I need to use triggered sampling to get a constant known sampling rate? Any ideas?

[RSF]

Thank you, Alex, for your input. I want to sample two inputs for 17.5 ms and then do DSP on the data. This requires a known sampling rate and since the 56F800E series are 60 MIPS DSP controllers I thought CW would be more straight forward to use. I will look into reading the A/D outside of a bean. Maybe I will have to use a faster conversion time to compensate for overhead to get the desired sampling rate.

Ray

[ProcessorExpert]

Hello,
The 56F8300E CPUs supports internal synchronization between ADC and a timer, which allows to set a diserid sampling time. Without this triggering it's quite difficult to compute the real sampling time (there are overheads for OnEnd interrupt code etc..)

The Processor Expert 2.97 contained in CodeWarrior 7.3 contains a
synchronization configuration wizard that allows to easily setup this synchronization :

- Add ADC bean into the project
- Configure the ADC bean channels, conversion time etc.
- Switch to the Expert mode of the Bean Inspector (using the Expert button)
- Then click on the '...' dialog button in the property 'Trigger
configuration wizard'
- Answer the wizard's quistions
- As the result a new timer initialization bean is created and preset to synchronize the ADC.
- Setup the 'Timer Load Register'.
This register controls the length of the period of the timer
output toggling.
Let's say you need 10kHz sampling and you have 32MHz IPBus clock.
For timer prescaler 1 and IPBus freq. 32MHZ, it will be: 32 MHz / 10kHz = 3200.
We need to divide this by two because the output has to toggle twice within one period. So the time will be 1600 IPBUs ticks.

- Generate code and place a code reading the value into the OnEnd event code of the ADC bean.

- In the main() function, the synchronization has to be enabled by calling
AD1_EnableIntTrigger(); method of ADC bean in the beginning of the main routine.

I hope that this will help.

best regards
Petr Hradsky
UNIS

[alex_spotw]

Hi:

Could you explain a little bit more what do you want to do? Sample two inputs every 17.5ms, or sample two inputs for 17.5ms at what sample rate?

You have to be careful, because the algorithm that I presented before works fine for one inout only, at the max rate. If you have two inputs, then, if you interleave the samples, then the effective sampling rate is halved.

It is possible for your application to sample one input for 17.5ms and then the other input for 17.5ms at the max sampling rate?

Regards,

ALex

[RSF]

Alex,

I am monitoring two 40 kHz transducers for 17.5 ms looking for echoes of a transmit pulse. The Nyquist rate is 80 kHz so I am looking at a sampling rate of 100 to 250 kHz. The higher the sampling rate the more memory will be needed to analyze the received data but the resolution has to be good enough to distinguish the signals using correlation. I am currently reading two analog inputs simultaneously in continuous mode. I start the continuous conversions, read and store the samples using the AD1_GetValue16 in the AD1_OnEnd code. Since the difference in the timing between the transducers is critical to my application I prefer this approach.

Feeding a 10 kHz signal from a signal generator into the ADC and calculating the samples per cycle I have tried different values for DIV in the ADC control register 2 and have calculated the following sampling rates:

DIV                 kHz

8                     233

10                   200

12                   185

15                   160

20                   133

30                   96

This was done using a 56F8323 on the 56F800DEMO board with a 60 MHz clock. I assume that this will translate directly to my target 56F8365 running the same code. I have not tried using the triggered approach suggested by Petr as yet. The triggered method should yield any needed sampling rate as apposed to just what you get playing with the value of DIV.

Ray

[alex_spotw]

Hi:

My point is that there will be always an overhead after taking a sample, because the processor has to transfer that sample somewhere into RAM Memory. The 56F8300E family ATD module has a internal buffer that can store up to 8 samples. You might want to take adavantage of that buffer
to minimize the overhead effects.

Regards,

Alex

[RSF]

Alex

I believe the ADC writes the results into the buffer and I read the buffer with the GetValue16. The buffer can hold the results from up to 8 inputs but I don’t think it can hold 8 conversions from one input and even if it can I would not want 8 fast conversions and a delay. I need a consistent sampling rate.

I am still analyzing the data I took using the DIV manipulation. If that is adequate for my project I will move on otherwise I will try the triggered approach.

Thank you Petr for your suggestions.

Ray

[alex_spotw]

Hi:

Processor Expert introduces a significan overhead to the ATD sampling process, which depending of your code could be 10 to 20 times the sampling rate.

The alternative that I use is not to use the Processor Expert routines to do the ATD Sample. I use the Bean for the configuration, and I have other functions that write directly to the ATD registers in the ATD Module. I know that this breaks the philosophy of the encapsulated Bean and the portability of the code, but it provides the fastest sampling rate.

Using polling, once you have the minimum code required to start a conversion, wait for the sample to be finished and store it in a buffer. I found that is is more efficient (time-wise) to construct the sample's histogram on the fly, rather than storing every sample because of the memory access (based on a HCS08 processor). My application can use better the histogram. The 56F8300E probably has better memory access times.

To obtain constant known sampling rates, you should measure the sampling rate including the overhead of starting the sample, and storing the result. This would give you the real sampling rate that you get with your processor. The ATD module still samples at 4us, but the overhead is taken into account.

YOu could have a blocking routine that do all the sampling for a period of time (if your application can use this scheme). This way you get a constant known sampling rate.

Regards,

Alex

Message Edited by alex_spotw on 2006-06-30 02:11 PM