FS26 SBC init delay

[kjy106906]

Hello

I have a question regarding the FS26 SBC.

Is more delay needed in the following situations?
Standby -> SPI wake up -> delay 1.5ms -> SBC init

For 1.5ms, I referred to the phrase below in the datasheet.

SPI chip select wake-up:
– When the SPI wake up is enabled, the device wakes up with any activity on the SPI bus (transition from high to low of CSB pin).
– In case of a SPI wake up, the first SPI command is ignored, and the FS26 will be ableto respond to the subsequent SPI commands after 1.5 ms.

However, init fails with 1.5ms.
Init succeeds with 10ms.

Is there an exact delay guide?

[guoweisun]

No fully understand you wrote:

 init fails with 1.5ms.
Init succeeds with 10ms.

Could you please give more explain?

[kjy106906]

Yes.

Standby -> SPI wake up -> delay 1.5ms -> Sbc_fs26_Init

-> return Not Ok

Standby -> SPI wake up -> delay 10ms -> Sbc_fs26_Init

-> return Ok

[guoweisun · Accepted solution]

Set this time above 7ms.

[kjy106906]

@guoweisun 

SBC Standby -> SPI wake up -> delay 1.5ms -> Sbc_fs26_Init

-> return Not Ok

SBC Standby -> SPI wake up -> delay 10ms -> Sbc_fs26_Init

-> return Ok

I don't know why you are talking about RSTB time.
If I put the SBC in Standby, the SBC will not become a POR.
When MCU do SBC SPI wakeup, RSTB has already been released.

[guoweisun]

---

I don't know why you are talking about RSTB time.
If I put the SBC in Standby, the SBC will not become a POR.
When MCU do SBC SPI wakeup, RSTB has already been released.

---

After wake up SBC state machine still follow below, detail in datasheet page25:

[kjy106906]

Yes.

It says "but maintained high during wake up from Standby" on it.

so 

SBC Standby (RSTB High) -> SPI wake up (RSTB High)-> delay 1.5ms (RSTB high) -> Sbc_fs26_Init(RSTB high) -> return Not Ok

RSTB is always high, so why is RSTB Release time and delay related?

Thank you

[guoweisun]

Although RSTB is high but the state machine still follow:

Default FS_OTP Loading->LBIST DONE->ENABLE Monitoring->ABIST1 test->enter INIT FS 

[kjy106906]

Very Thank you I understood

[guoweisun]

I think below process:

Standby -> SPI wake up -> delay 1.5ms at same time the fail safety mechanism continue to flow as below picture if no failure will stop in INIT phase  -> SBC init