We are creating an example model using the NXP Model-Based Design Toolbox (MBDT) Version 3.2.0 for MPC57xx Series processors to create an example interfacing with the MSDI chip CD1030 over SPI bus from the MPC5777C processor, see the attached model.
We are able to send the 32-bit "SPI Check" message [0x00 0x00 0x00 0x00] as uint8(4) and get the expected response 0x00123456 from the "SPI Master Transfer" block.
However, when we try to read the switch status SP or SG registers using messages [ 0x3C 0x00 0x00 0x00 ] and [ 0x3E 0x00 0x00 0x00 ] respectively, we a response 0x3fbadbad. Seeing "bad" plainly visible repeated twice in the response (as Hexspeak) suggests something is terribly wrong.
By comparison, the response from the SPI Check message is as expected:
The simplified top-level model:
And the state chart that passes messages to the CD1030 MSDI chip:
The SPI Config Block used Continuous Transfer and Frame Size 8:
The above configuration was set based on an answer to a previous question:
Request for HSD/LSD/MSDI Communication Examples for MPC5775B BMS and VCU Reference Design
The above was extremely helpful, but going forward brings us to a new challenge.
Further guidance would be greatly appreciated. Thanks.