mpc5777c etpu setting

cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 

mpc5777c etpu setting

674 Views
chanu
Contributor I

Hi, I have a problem with setting etpu about mpc5777c.

The etpu pin setting for A,B,C about Top and Bottom is gpio 115,116,117,118,119,124.

Etpu pwm made with mcal doesn't come out, so I'm trying to randomly make two pwm master channels and output them, but I'm not sure how to configure them, so I'm asking for help.

 

 

 

0 Kudos
4 Replies

644 Views
chanu
Contributor I

pin setting The 5777c etpu pin setting is shown in the following figure. As far as I know, a,b,ctop,bottom should act as complementary after allocating one pwm master channel of etpu Think.

etpu settingBut the pwm output didn't come out, so I arbitrarily modified the code to separate and output top and bottom.

duty output codeI'm trying to output the duty ratio to be deformed for the Vref output, but if I do this, it only comes out to 82V, not 92V.

So, the conclusion is that when using one PWM master channel and complementary operation, I want to set pwm output and PWM master channel to top and bottom single output, and then set etpu as same as output, so I want to get help.

 

 

0 Kudos

643 Views
chanu
Contributor I

123.pngdd.pngddddee.png

0 Kudos

575 Views
nxa17216
NXP Employee
NXP Employee

Hello,

not sure if you have performed all the steps needed to get the eTPU PWMM funciton up and running. I have noticed one thing in your channel assignment - for phase C your configuration of base and complementary channels is not correct, complementary channel always have to be base channel +1.  Here is what you need to configure with examples:

1. perform the eTPU PWMM defines in etpu_gct.h:

  • PWMM uses either 4 channels (in case of single channels) or 7 channels in case of complementary channel configuration as shown in the example below. There is a condition that all the PWMM channels master and phases have to be located at the same engine. There is no dedicated channel number for Master channel. For complementary channel configuration there is a restriction that complementary phase pair have to be assigned to consecutive channels.
    • Phase X base → eTPU n channel
    • Phase X complementary → eTPU n+1 channel
    • example configuration:

nxa17216_0-1693287163388.png

  • ISR and DMA requests configuration – PWMM Master channel is only capable of generation interrupt request – missing update interrupt. This request is generated when no update of input values come before frame and center updated.

nxa17216_1-1693287270624.png

  • Enable global variable access - to make the eTPU structures being visible outside the gct files to be accessible from main function:

nxa17216_2-1693287594171.png

  • Declare function prototypes:

nxa17216_3-1693287645878.png

2. perform function configuration in etpu_gct.c

  • include necessary files:

nxa17216_4-1693287932031.png

  • Define PWMM instance structure – use definitions of PWMM channels from etpu_gct.h for particular functionality assignment. Note that only PWMM Master channel and phase base channels have to be defined here, in case of complementery channels are configured the eTPU function presumes the complementary channel to be the base + 1. Configure the priority of the PWMM function, specify the type of the phases (single/complementary pairs) and set the  polarity for phases, whereas in case of complementary pairs the polarity can be configured independently for base and complementary channels. Start offset parameter determines the time of first PWMM frame-time after the eTPU time base is enabled. Channel parameter base address cpba can be configured for a particular address within the eTPU data memory or it can be configured as 0 – in that case cpba will be allocated automatically. This parameter determines the address where PWMM channel parameters are stored within eTPU data RAM.

nxa17216_5-1693288582833.png

  • Define PWMM configuration structure – use predefined macros to configure intended functionality. All the possible options are listed in etpu_pwmm.h in comments and described in PWMM-doxydoc.chm file. Parameters of the configuration structure can be changed during runtime and are applied in upcoming PWMM update

nxa17216_6-1693288725404.png

  • Define PWMM inputs structure – this structure holds input parameters for phases A, B and C used for update of the generated duty cycles. This structure can remain empty during initialization. Values in this structure will be applied in Frame or in both Center and Frame update – based on update configuration

nxa17216_7-1693288889868.png

  • Define PWMM states structure - this structure contains outputs representing internal states of the PWMM function. This structure is not to be initialized. It is used to get information about the PWMM status.

nxa17216_8-1693289032242.png

  • Implement the eTPU initialization function: my_system_etpu_init() This function consists of 2 parts. The first one is eTPU engine configuration using my_etpu_init structure – this is already implemented in etpu_gct.c template, it does not need to be modified. The second part configures all eTPU channels needed by PWMM function using appropriate API calls. For PWMM, the call of fs_etpu_pwmm_init(…) defined in etpu_pwmm.h needs to be added.

nxa17216_9-1693289162134.png

3. Get the eTPU PWMM function running by calling the initialization and start routines in the main function. You can then perform the update of the duty cycles by changing pwmm_inputs structure values in endless loop for example (below is just example, adjust that to your application)

nxa17216_10-1693290528891.png

 

0 Kudos

650 Views
petervlna
NXP TechSupport
NXP TechSupport

Hello,

Could you explain the issue more closely? Are you using any configuration tool? Any drivers? Or the code is written by you?

Which version of SW?

From the information you have provided I am not able to help you.

Furthermore the functions of SIU is explained in Chapter 8\ System Integration Unit (SIU, SIU_B) reference manual and its attached IO spreadsheet.

Best regards,

Peter

0 Kudos