mpc5744 could not work under 60 degree temperature.

[hansonhe]

Dear,

One of customer use MPC5744, their product could not work well under 60 degree temperature, it could work well under normal indoor temperature, could you help review the code? Thanks.

We doubt the PLL clock configure. 

[hansonhe]

We find their code use two times for the clock configuration in boot and application code, which are same for clock configuration. After comments below code in application code, the issue is closed, we want to know whether below code could not config two times? They use external 8M clock with 27pf cap.

MC_CGM.AC3_SC.B.SELCTL = 0x01; //connect XOSC to the PLL0 input
MC_CGM.AC4_SC.B.SELCTL = 0x01; //connect XOSC to the PLL1 input

//PLLDIG.PLL0DV.R = 0x3008100A; // PREDIV = 1, MFD = 10, RFDPHI = 8, RFDPHI1 = 6
PLLDIG.PLL0DV.B.PREDIV=1;
PLLDIG.PLL0DV.B.MFD=50;
PLLDIG.PLL0DV.B.RFDPHI=8;
PLLDIG.PLL0DV.B.RFDPHI1=8;

MC_ME.RUN0_MC.R = 0x00130070; // RUN0 cfg: IRCON,OSC0ON,PLL0ON,syclk=IRC

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

// PLLDIG.PLL1DV.R = 0x00020014; // MFD = 20, RFDPHI = 2
MC_CGM.AC4_SC.B.SELCTL=0b11; //PLL0_PHI1 selected as input of PHI1
PLLDIG.PLL1DV.B.MFD=16;
PLLDIG.PLL1DV.B.RFDPHI=2;

MC_ME.RUN_PC[0].R = 0x000000FE; // enable peripherals run in all modes
MC_ME.RUN0_MC.R = 0x001300F4; // RUN0 cfg: IRCON, OSC0ON, PLL1ON, syclk=PLL1

MC_CGM.SC_DC0.R = 0x80030000; // PBRIDGE0/PBRIDGE1_CLK at syst clk div by 4 ... (50 MHz)

// Mode Transition to enter RUN0 mode:
MC_ME.MCTL.R = 0x40005AF0; // Enter RUN0 Mode & Key
MC_ME.MCTL.R = 0x4000A50F; // Enter RUN0 Mode & Inverted Key
while (MC_ME.GS.B.S_MTRANS) {}; // Wait for mode transition to complete
while(MC_ME.GS.B.S_CURRENT_MODE != 4) {}; // Verify RUN0 is the current mode

[petervlna]

Hi,

You are using 8MHz crystal as input. So according to the reference manual:

PREDIV = 1 -> 8/1 = 8MHz

MFD = 50

VCO = MFD * Input clock*2 = 50*8*2 = 800MHz

RFDPHI = 8

so your PLL0PHI clock = 800 / 8 = 100MHz

PLL0PHI1 = 50MHz

Now to the clock for PLL1

PLL1 = 50* 16  / 2 /2 = 200MHz

Maximum allowed PLL1 clock is 200MHz.

I see no issue here. Maybe you can try different division combination to achieve desired clocks.

Peter

[hansonhe]

Peter,

My questions is that, 

1. Whether clock setting code could config two times? Such as in boot code and application code. 

2. What is the temperature influence about two times clock configuration? 

2. If code need config two times for the clock, how to restore the clock configuration mode in boot code before switch to application code? 

 Thanks.