eMIOS in MPC5746R

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eMIOS in MPC5746R

1,268 Views
flyskyr丶
Contributor III

I want to use eMIOS to produce PWM in MPC5746R, but it can't work...

I need help.

Hardware environment:

MPC57xx Motherboard && MPC5746R-176DC

My Init program:

 MC_CGM.AC5_SC.B.SELCTL =2; //connect PLL0 on AUX_5

 MC_CGM.AC5_DC1.R = 0x80000000 | 0x10000; //eMIOS

eMIOS_1.MCR.B.GPREN = 0; /* Disable global pre-scaler (reset default) */
eMIOS_1.MCR.B.GPRE = 99; /* Divide 100 MHz clock to module by 100 */
eMIOS_1.MCR.B.FRZ = 0; /* No Freeze channel registers in debug mode if channel FREN=0 */

eMIOS_1.C23.R = 0x0; /* Disable channel pre-scaler (reset default) */
eMIOS_1.A23.R = 250; /* OPWFMB mode: duty cycle count */
eMIOS_1.B23.R = 500; /* OPWFMB mode: period will be 500 counts */
eMIOS_1.CNT23.R = 1; /* OPWFMB start counter between 1 & B register value*/
eMIOS_1.C23.B.MODE = 0x58; /* Output Pulse Width & Frequency Modulation*/
eMIOS_1.C23.B.EDPOL = 1; /* Output polarity on A match */
eMIOS_1.C23.B.UCPRE = 0; /* Pre-scale channel clock by 0+1=1 */
eMIOS_1.C23.B.UCPREN = 1; /* Enable pre-scaler */

SIUL2.MSCR0_255[127].B.SSS = 0x03; /* set PH15 as eMIOS1_23 */
SIUL2.MSCR0_255[127].B.ODC = 2; /* set as 3:open-drain 漏极开路 2:推挽输出 */
SIUL2.MSCR0_255[127].B.OERC = 1; /* Full strength slew rate */

eMIOS_1.MCR.B.GPREN = 1; /* Enable global pre-scaled clocks */
eMIOS_1.MCR.B.GTBE = 1; /* Enable global time base */

Is my configuration problematic?

Tags (2)
2 Replies

821 Views
jamesmurray
Contributor V

I found that the eMIOS register definitions supplied by NXP were wrong and have been using my own definition instead.

See : S32DS EmbSys registers mixup MPC5746R 

I would like to know if NXP are going to release an updated MPC5746R.h to fix the number of errors that I have reported. (eTPU, eMIOS, LINFLEX, CAN)

James

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821 Views
PetrS
NXP TechSupport
NXP TechSupport

Hi,

the eMIOS channel setting looks correct.

Is the eMIOS clock enabled through Mode Entry module? Check ME_PS7 register. Also within debugger check if the eMIOS ch23 registers are written and counter is running.

BR, Petr