S32DS EmbSys registers mixup MPC5746R

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S32DS EmbSys registers mixup MPC5746R

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jamesmurray
Contributor V

First off, I really like the EmbSys register view, it's great!

However, when configured for MPC5746R with e200 core, there appear to be a few inconsistencies. (See attached embsys1.png)

1. eTPU registers aren't all grouped under eTPU like the other modules. (See attached embsys2.png)

2. eMIOS is confusing and appears to use the wrong addresses? (See attached embsys3.png)

I would expect to see eMIOS1 channel 8 registers cascaded as eMIOS -> eMIOS_1 -> eMIOS_1_UC08 but it seems they are presented as eMIOS -> eMIOS_1_UC08 etc.

Then within each channel, it looks like the other channels are there as well???? (See attached emios2.png)

Now, the addresses...  from MPC5746RRM.pdf (See attached emios1.png)  I would expect eMIOS1 channel 8 register B to be at:

eMIOS base + channel 8 offset + register B offset

0xFBE64000 + 0x120 + 0x004

= 0xFBE64124

From MPC5746R.h

#define eMIOS_1 (*(volatile struct eMIOS_tag *) 0xFBE64000UL)
#define eMIOS_1_UC08 (*(volatile struct eMIOS_tag *) 0xFBE64340UL)

From the ref manual, I thought 0xFBE64340UL is in reserved space?

From the EmbSys view, it thinks that UC08 register B is at 0xFBE64464

It's also a shame that the register naming has changed from the way MPC563m.h had it. Previously, the channels were referred to using arrays e.g.

EMIOS.CH[8].CBDR.R

now it appears to be:

eMIOS_1.B20.R

without the array and with a definition for each channel.

James

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jamesmurray
Contributor V

There have been a number of new ARM releases of S32DS. Any chance of showing PowerPC some love and putting out a new release which fixes the bugs I've reported in MPC5746R.h? (eTPU, eMIOS, LINFlex, CAN)

James

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jiri_kral
NXP Employee
NXP Employee

Well, the offset mismatch is still present - even with latest update. I'll ping the dev team. Hope the issue will be fixed in next release - the ticket was created during code freeze phase for v2017.R1. 

Jiri

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jiri_kral
NXP Employee
NXP Employee

Hi James, 

I already created ticket for your issue last year. I didn't check if the offset mismatch is still present in S32DS Power v2017.R1 with updates. I'll do that. 

Jiri

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jamesmurray
Contributor V

NXP - any thoughts on this?

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