The crossbar switch allows both the DMA (or other master) and the core to access the bus slaves simultaneously, this greatly speeds up execution time and performance. Note the DMA (or other master) and the core cannot access the same peripheral at the same time an arbitration scheme is in place to take care of this instance should it occur. It has nothing to do with interrupts or interrupt controller, XBAR is a crossway of internal busses (data and instructions).
It is quite common to leave XBAR setting untouched, but it may happen in certain situations that changing priorities is necessary, for instance if one master (core 0) continuously accessing certain slave and other master (core 1) cannot get free time slot to access the same slave. For example, choosing of round-robin arbitration scheme would solve this issue and both cores would have equal chance to access the slave.
XBAR is a base of all MPC5xxx devices.
