TRK-MPC5606B : SPI daisy chain for AD5293 digital pot

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TRK-MPC5606B : SPI daisy chain for AD5293 digital pot

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ninguc
Contributor I

hello all

 

i'm facing problem in Implementing SPI daisy chain for   AD5293 digital pot, the connection as shown in bellow fig.

here i want to shift my data until to 48 clock cycle with respect i need to make DSPI1_CS0_BAR pin should be low until 48 clock cycle  to read/write  DPOT data. Is it possible to make DSPI1_CS0_BAR pin  low for 48 cycle. if yes how can i make it low for 48 clock  cycle.

102904_102904.pngpastedImage_0.png

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

You can set the DSPI module for 16bit data transfer and send 3 words with Continuous selection format.

That is set the CONT bit in the first two SPI commands and clear it in last one.

See more in the DSPI chapter of the device Reference manual.

Hope it helps.

BR, Petr

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ninguc
Contributor I

Hello Petr,

SCK is not the problem here. We need to keep the Chip Select low for 3 x 16 Data out transfers. But i observe is that the chip select goes high and then goes low after each 16 bit transfers, and this is the problem. When we put the first 16bit data into the push register and check for transfer complete flag and once it is transmitted then we push the second 16bit data but here the chip select goes high which is undesired. Below is the snapshot of the data sheet of AD5293. In our application we are using 3 AD5293 in daisy chain configuration. We configured clock to be continuous with CPOL = 0, CPHA =1 and 32Mhz dspi pheripheral clock.

Kindly let us know how can we control the Chip Select Line for 48 bit data transfer.

pastedImage_0.png

I did not understand this below diagram in the manual. Does the CS goes high after 1 transfer?

pastedImage_4.png

Regards,

Ningu

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

The Figure 26-24 seems to be wrong.  If CONT=1 is set for first word the CS remains asserted, there is no CS deassertion in general. However it can happen if the TX FIFO becomes empty when pushing commands to the FIFO. Please read the NOTE  at chapter 26.6.5.5. of the device Reference Manual.

BR,

Petr.

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ninguc
Contributor I

Hello,

Thanks for the information.

After much debugging we were able to resolve most of the things except one, that is when we write into the digital pot 3 and after read back it always reads as zero.

Data written into Digital Pot 1 and Digital Pot 2 were able to successful read whatever we have written.

Sequence :

Write to Digital Pot1 with PUSH Contents : 0x8001XXXX

Write to Digital Pot2 with PUSH Contents : 0x8001XXXX

Write to Digital Pot3 with PUSH Contents : 0x0001XXXX

POT 3 Read

Then we do a dummy PUSH with 0x0001XXXX command to get the POP contents of Digital Pot3

POT2 Read

Then we do a dummy PUSH with 0x8001XXXX command.

Then we do a dummy PUSH with 0x0001XXXX command to get the POP contents of Digital Pot2

POT1 Read

Then we do a dummy PUSH with 0x8001XXXX command.

Then we do a dummy PUSH with 0x8001XXXX command.

Then we do a dummy PUSH with 0x0001XXXX command to get the POP contents of Digital Pot1

When we do this the POP contents of Digital Pot 1 is always zero or missed.

We verified the contents of the SPI registers and it all looks good on the transmission.

Please give us hint where to look in to resolve this behaviour. Any advice on debugging this issue would be great help.
Any design advice is for such daisy chain configuration is also appreciated.

we followed bellow design:

pastedImage_5.png

Kindly check the configuration below.

Below is my DSPI_0 configuration :

/*..................Testing.......................*/

void initModesAndClks(void)

{

  ME.MER.R = 0x0000001D;          /* Enable DRUN, RUN0, SAFE, RESET modes */

                                  /* Initialize PLL before turning it on: */

  CGM.FMPLL_CR.R = 0x02400100;    /* 8 MHz xtal: Set PLL0 to 64 MHz */

  ME.RUN[0].R = 0x001F0074;       /* RUN0 cfg: 16MHzIRCON,OSC0ON,PLL0ON,syclk=PLL */

  ME.RUNPC[1].R = 0x00000010;  /* Peri. Cfg. 1 settings: only run in RUN0 mode */

  ME.PCTL[4].R = 0x01;            /* MPC56xxB/P/S DSPI0:  select ME.RUNPC[1] */

  ME.PCTL[5].R = 0x01;            /* MPC56xxB/P/S DSPI1:  select ME.RUNPC[1] */

  ME.PCTL[68].R = 0x01;           /* MPC56xxB/S SIUL:  select ME.RUNPC[0] */

                                  /* Mode Transition to enter RUN0 mode: */

  ME.MCTL.R = 0x40005AF0;         /* Enter RUN0 Mode & Key */

  ME.MCTL.R = 0x4000A50F;         /* Enter RUN0 Mode & Inverted Key */

  while (ME.GS.B.MTRANS) {}     /* Wait for mode transition to complete */

                                  /* Note: could wait here using timer and/or I_TC IRQ */

  while(ME.GS.B.CURRENTMODE != 4) {} /* Verify RUN0 is the current mode */

}

void initPeriClkGen(void)

{

/* Use the following code as required for MPC56xxB or MPC56xxS:*/

  CGM.SC_DC[1].R = 0x81;   ;      /* MPC56xxB/S: Enable peri set 2 sysclk divided by 1 */

}

void disableWatchdog(void)

{

  SWT.SR.R = 0x0000c520;     /* Write keys to clear soft lock bit */

  SWT.SR.R = 0x0000d928;

  SWT.CR.R = 0x8000010A;     /* Clear watchdog enable (WEN) */

}

void initDSPI_0(void)

{

  DSPI_0.MCR.R = 0x80010001;     /* Configure DSPI_0 as master */

  DSPI_0.CTAR[0].R = 0x7A0A7727; /* Configure CTAR0  */

  DSPI_0.MCR.B.HALT = 0x0;     /* Exit HALT mode: go from STOPPED to RUNNING state*/

  SIU.PCR[13].R = 0x0604;        /* MPC56xxB: Config pad as DSPI_0 SOUT output */

  SIU.PCR[12].R = 0x0103;        /* MPC56xxB: Config pad as DSPI_0 SIN input */

  SIU.PCR[14].R = 0x0604;        /* MPC56xxB: Config pad as DSPI_0 SCK output */

  SIU.PCR[15].R = 0x0604;        /* MPC56xxB: Config pad as DSPI_0 PCS0 output */

}

void initDSPI_1(void)

{

  DSPI_1.MCR.R = 0x00010001;     /* Configure DSPI_1 as slave */

  DSPI_1.CTAR[0].R = 0x780A7727; /* Configure CTAR0  */

  DSPI_1.MCR.B.HALT = 0x0;     /* Exit HALT mode: go from STOPPED to RUNNING state*/

  SIU.PCR[68].R = 0x0903;        /* MPC56xxB: Config pad as DSPI_1 SCK input */

  SIU.PSMI[7].R = 1;             /* MPC56xxB: Select PCR 68 for DSPI_1 SCK input */

  SIU.PCR[36].R = 0x0103;        /* MPC56xxB: Config pad as DSPI_1 SIN input */

  SIU.PSMI[8].R = 0;             /* MPC56xxB: Select PCR 8 for DSPI_1 SIN input */

  SIU.PCR[37].R = 0x0604;        /* MPC56xxB: Config pad as DSPI_1 SOUT output*/

  SIU.PCR[69].R = 0x0903;        /* MPC56xxB: Config pad as DSPI_1 PCS0/SS input */

  SIU.PSMI[9].R = 2;             /* MPC56xxB: Selec PCR 15 for DSPI_1 SS input */

}

Let me know if you need some detailed information we can provide a diagram for better explanation of the issue.

Regards,

Raghavendra P

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

Not really sure. At one sentence you wrote digital pot 3 read returs zero. On other one it appears on digital pot 1. So wich one returns wrong/zero data.

I can recommend to see the SPI lines with scope and display full 48bit frame. Also RDY signal could be useful to display.

I understand that for reading the register in this daisy chain connection you should send 2 48bit frames. First with commands 2 the second one with commands 0. After second frame the SPI RX FIFO should contains all 3 pot’s register values.

So I expect these sequences:

//Prepare data read from RDAC registers

PUSH Contents : 0x80010800

PUSH Contents : 0x80010800

PUSH Contents : 0x00010800

//3 times Dummy POP read

POP Contents : dummy

POP Contents : dummy

POP Contents : dummy

// NOP commands send

PUSH Contents : 0x80010000

PUSH Contents : 0x80010000

PUSH Contents : 0x00010000

//3 times POP reads to get RDAC values

POP Contents : pot 3

POP Contents : pot 2

POP Contents : pot 1

BR, Petr

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raghavendrapura
Contributor I

Hello Petr,

Still we are not able to resolve this issue :

Could you please write me a pseudo code for Write and Read so that i can try to test it :

Write : Write of all three AD5293 with 3 different data in each

Read : Read of all three AD5293

Regards,

Raghavendra P

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PetrS
NXP TechSupport
NXP TechSupport

Hi,

Did you try to use the scope to see the real signals on the DSPI lines and POTs RDY signal? What is the result?

Regarding the DSPI Init; from the first picture I see  POTs are connected to DSPI1, however in your code you set DSPI0 as master and DSPI1 as Slave. This is wrong, Master have to drives the POTs. Reconfigure DSPI1 if it is really used for driving POTs. Use the CPOL=0 and CPHA=1 configuration for CTAR register. Other CTAR’s field setting have to be selected with respect of POTs datasheet. 

The read sequence I outlined last time. The write sequence could be following:

//Enable update of wiper position. Must be used after power-up if RDAC is write protected

PUSH Contents : 0x80011802

PUSH Contents : 0x80011802

PUSH Contents : 0x00011802

//Write 0x100 to the RDAC register. Wiper moves to ¼ full-scale position.

PUSH Contents : 0x80010500

PUSH Contents : 0x80010500

PUSH Contents : 0x00010500

Note: The RDY pin can be used to monitor the completion of this RDAC register write command. After issuing the readback command, the RDY pin can also be monitored to indicate when the data is available to be read out on SDO in the next SPI operation. Instead of monitoring the RDY pin, a minimum delay can be implemented when executing a write or read command (see Table5 of the POTs datasheet).

Note: POTs SDO is an open-drain pin that requires a pull-up resistor if this pin is used. Users may need to increase the clock period, because the pull-up resistor and the capacitive loading at the SDO-to-DIN interface may require additional time delay between subsequent devices. CTAR must be properly set.

BR,Petr

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