Supervisor mode protection for DMEM

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Supervisor mode protection for DMEM

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yixinwu
Contributor I

Hello community,

I want to use DMEM under supervisor mode by configuration of DMEMCTL1 and MPU as followed.

 

  asm("e_lis r3, 0xAAAA");
  asm("e_or2i r3, 0xAAAA");
  /* dcr 498: DMEMCTL1, all S/U access to 4 DMEM quadrants according to MPU */
  asm("mtdcr 498, r3");


  //DMEMSREC       0x5080C000 -0x5080FFFF          
  VALID|SELECTMPU|ENTRY4|SW|UXR|SXR,           //0xA0040700
  PID_ALL,              //0                           
  ADR_DMEMSREC_END,     //0x5080FFFF
  ADR_DMEMSREC_START    //0x5080C000

But I can still write in the address from 0x5080C000 to 0x5080FFFF, when I am in user mode. What have I done wrong?

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lukaszadrapa
NXP TechSupport
NXP TechSupport

I did quick test and I can see that it works as expected. What I did:

1. I wrote 0xAAAAAAAA to DMEMCTL1 like this:

       e_lis r3, 0xAAAA
       e_or2i r3, 0xAAAA
       mtdcr 498, r3

2. I initialized CMPU. This is for DMEM:

    e_lis  r3, 0xA003 //# VALID=1, INST=0, SHD=0, ESEL=3
    e_or2i r3, 0x0700 //# UW=0, SW=1, UX/UR=1, SX/SR=1
    mtspr  mas0, r3
    e_lis  r3, 0x0000
    e_or2i r3, 0x0000
    mtspr  mas1, r3
    e_lis  r3, 0x5080
    e_or2i r3, 0xFFFF
    mtspr  mas2, r3 //0x5080_FFFF
    e_lis  r3, 0x5080
    e_or2i r3, 0x0000
    mtspr  mas3, r3 //0x5080_0000
    mpuwe
    mpusync

pastedImage_1.png

3. CPU runs in supervisor mode. I wrote DMEM to test it:

*(unsigned int*)0x50800000 = 0xAAAABBBB;

This works.

4. I set MSR[PR] to enter user mode. If I wrote the DMEM as in step (3), exception is triggered.

So, everything is OK from my point of view.

Regards,

Lukas

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yixinwu
Contributor I

Thank you very much! I will test this again.

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Hi,

which device is that?

Regards,

Lukas

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yixinwu
Contributor I

Sorry, I forgot to say. It is MPC5744P.

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lukaszadrapa
NXP TechSupport
NXP TechSupport

Thanks, let me check that.

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