SPI communication about MPC5644

[ZEROOO]

Hi

    Using MPC5644 to configure SPI for the host, I found that the polarity required to be set to 1 in the manual of the external chip for communication, but I could continue to communicate after I mistakenly set it to 0. I would like to ask how this happened, why can I communicate normally no matter what the polarity is?

[FaithWade]

Out test results show a repeated error while programming M95128-R EEPROMs. The EEPROMs are located on separate panels. To program these SPI devices, we use relays and the Cheetah SPI Host Adapter. We are using LabVIEW to control the relays, which select the cables to connect to the CS, MOSI, MISO, and CLK of the desired panel. Here is a diagram of our setup: 

Our issue is we are having a repetitive, consistent failure. Everything runs smoothly and then shortly after an error occurs and one of the panels fails. After investigation, we have assessed that we are not damaging any of the panels as we originally suspected. In fact, despite the failures that repeatedly occur in our setup, we can program the panel EEPROMs separately with a different programming device.

We have also ruled any hardware problems with the Cheetah adapter. We have several Cheetah adapters, and we have achieved the same results with each Cheetah adapter.  

[PetrS]

Hi,

from memory datasheet I see, it can be driven by a microcontroller with its SPI configured in either of the following two modes:
• CPOL = 0, CPHA = 0
• CPOL = 1, CPHA = 1 
To this should be kept.

From your description I do not know where the MPC5644 is located and what config is used.

BR, Petr

[PetrS]

Hi

can you specify the external device you have?
Ideally measure SPI signals with scope/analyzer and compare it with device protocol specification.
This could give more insight into why communication works for more configurations.

BR, Petr

[ZEROOO]

Hi

    The peripheral chip uses stmicroelectronics L9305.I checked the polarity and phase of MPC5644:Polarity=0, Phase=1.Below is the spi waveform of 9305 collected:

Although the communication can be carried out normally according to the above polarity and phase configuration, it is found that the idle state of 9305 chip manual is 1, as shown in the figure:

Therefore, is the key configuration of MPC5644 spi set according to the host or slave? At present, it seems that it has nothing to do with slave, please help to confirm whether it is so.

[PetrS]

Hi,

master should use SPI mode that is accepted by connected slave.

BR, Petr

[ZEROOO]

Hi

    When setting the master polarity, the opposite polarity is set. The slave machine requires a high level to be idle, but is set to a low level to be idle. In this way, the communication between the master and slave machines is not affected

[PetrS]

Hi,

the given L9305 spi timing figure should correspond to CPOL=0/CPHA=1 mode.
After device is selected clock is low and first (rising) edge shifts data and second edge (falling) is sampling data, that is setting with CPOL=0/CPHA=1, which is same as your MPC5644A has.

BR, Petr