I am trying to test the functionality of MPC5777C EIM(Error Injection Module) and ERM(Error Reporting Module). I have configured to inject errors in the PRAMC_0 and PRAMC_1 channels in the EIM. When I am doing a read access in System RAM at address 0x4000_0000(the memory controlled by PRAMC_0), I would expect that an error be reported in the PRAMC_0 channel in the ERM. However, I am seeing that the error is being reported in the "Core0 data" or "Core1 data" channels(channel numbers: 14,16) in the ERM depending on where my build is loaded and not in the PRAMC_0 channel. On the other hand, when I do a write to the memory, I could see errors being reported in the PRAMC channel in the ERM and nothing reported in "Core data" channels. Could you please explain the reason for this behaviour?
EIM injects error to the particular RAM array bus, so it is being detected by the side affected by this error.
If it is write (thus transfer from Core0 to PRAMC_0 with error on the way), it’ll be detected by PRAMC_0.
If it is read (thus transfer from PRAMC_0 to Core0 with error on the way), it’ll be detected by Core0.
If you see more errors in more ERM channels at once, if could be possibly caused by enabled cache memory.