MPC5777c, eTPU: input pins configuration

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MPC5777c, eTPU: input pins configuration

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969件の閲覧回数
cedric_toncanie
Contributor I

Hi,

On MPC5777  we configures eTPU B channel 0-1 as inputs (PCR147 -148) with PA = Primary function and IBE set to 1.

SIU PCR 147 Configuration Register:

pastedImage_2.png

Despite state changes on eTPU inputs pins, we still see 0 inside CSCR.IPS. Like there was no activity on the pins.

eTPU B CSCR Register:

pastedImage_1.png

We are able to play on the output pins. Our ETPU source code is running perfectly on MPC5644A.

ETPU B Configuration Register:

pastedImage_3.png

ETPU B Time Base Configuration Register:

pastedImage_4.png

Do you have any suggestions about maybe a missing SIU/ETPU configuration ?

Best Regards,

Cedric

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785件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

This is probably caused by IGF filter, which is placed between pad and some eTPU channels.
See chapter 39.1.3 “IGF interaction with other modules” of the device RM for more info. By default the IGF is in configuration mode (MCR[FGEN]=0) and the filter output is kept at logic '0' state. You can enable the filter by setting FGEN bit. By default, bypass mode is selected so enabling the IGF should be enough to see transitions on the eTPU channel.

From Table 39-3 you can see IGF_1 channels 17-31 are mapped to ETPUB0-14.

BR, Petr

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785件の閲覧回数
cedric_toncanie
Contributor I

Thank you Petr. It solved my issue. 

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786件の閲覧回数
PetrS
NXP TechSupport
NXP TechSupport

Hi,

This is probably caused by IGF filter, which is placed between pad and some eTPU channels.
See chapter 39.1.3 “IGF interaction with other modules” of the device RM for more info. By default the IGF is in configuration mode (MCR[FGEN]=0) and the filter output is kept at logic '0' state. You can enable the filter by setting FGEN bit. By default, bypass mode is selected so enabling the IGF should be enough to see transitions on the eTPU channel.

From Table 39-3 you can see IGF_1 channels 17-31 are mapped to ETPUB0-14.

BR, Petr