I'm using MPC5777c dev board, and working on SPI communication with using interrupts. MCU adjusted as Master, and it can communicate with a slave. Problem is about receiving operation.
When I read a information from the slave I must send a OP code and a few dummy messages. The Dummy messages is for generating SCK. I use RFDF and TCF to generate interrupt. My aim, enable RFDF_EN bit only when dummy messages sent. I created an algorithm to do that. If OP code is about reading operation, and next message to be sent dummy, enable RFDF_EN, else disable RFDF. also I clear the RX fifo in every condition.This conditions is before the writing message to PUSH register of SPI. The Problem is I always read an zero message before actual message(s). there are a few screen shots from my code and debug. How Can I fix this issue?
so within a TCF interrupt you halt transfer, flush RXFIFO, enable/disable RX ISR, store new word into PUSHR, start transfer. And RFDF ISR just reads RXFIFO value. This looks little bit complicated.
You can try to have RFDF ISR still enabled, so read every word. Then use TFFF to fill TXFIFO. Enable TFFF interrupt when transfer should be started, within TFFF ISR load PUSHR, before last word in frame disable TFFF ISR
BTW what is a baudrate and transfer format?
firstly thanks for response. according to my settings boudrate is about 3kbps. this is not final boudrate to be used. when I get stable communication I will set boudrate to faster one. also core clock frequency is 100MHz, per_clock is 40MHz, and FM_PER_CLK is 100MHz
In every SPI frame I'm sending 8 bit. but messages occur from different number of byte.( 1,2,4,5, and 33 byte including OPCODE)
I have already tried similar algorithm to your advice, with using TFFF, EOQF, RFDF. TFFF is used for sending messages which size is larger than 4. for smaller than 4 byte I did not enable the TFFF_EN. EOQF is used for sending next message and RFDF for receiving. But opitimum design is implemented using TCF and RFDF. My problem is not complexity, the problem is receiving unexpected zeros even through RXFIFO flushed and RFDF just enabled.
what if FIFO is disabled at all?
Or you can try to add DMA if it is applicable for application.