The current circuit of the MPC5777C EVB contains a SRAM (CY7C1347G-166AXC), which samples data and adress with the rising edge of the clock. We assume that all dedicated chip selects /CS for the SRAM are active for the following described process. The MPC enables the SRAM internal adress latching process with /TS and a rising edge on the EBI clock. /TS is only active in the first clock cycle of the transaction and therefore only inside the adress phase. After the adress phase /TS is deactivated and the MPC switches to the data phase. /OE is asserted in a read cycle and /WEx is asserted while a write cycle. /OE and /WEx are also read with the rising edge of the EBI clock.
The EVB uses a external latch to freeze the state on the muxed bus for the Pins A0 to A12 on the SRAM. The external latch gets transparent with the activation of ALE latchs after the deactivation of ALE. ALE is only activ for a duration of 6.5ns inside of the adress phase.
Our timing analysis shows that the SRAM latchs the adress internally from the MPC with the help of /TS and the rising edge of the CLK as described above. After that the internal latching mechanism inside of the SRAM is disabled and therefore it doesn't matter what state we have on the adress Pins of the SRAM. The external latch prevents a change of state on the adress pins of the SRAM while the data phase. But since the state doesn't matter the external latch is not necessary.
We tried to vaildate our assumptions with the EVB of the MPC5777C.
We set the ALE-Signal on permanent high with the help of the GPIO[299]-function on PIN P24. Therefore the external latch on the EVB is set to a permanent transparent mode. Now the adress pins of the SRAM see any effects caused by the switched muxed bus (address to data, to see any violation of address hold time). The only thing the latch can contribute in this state is a signal delay and a reduction of the capacitive load on the EBI. We verified the permanent high on ALE with an oscilloscope. Now we should have the exact configuration we proposed in our second post. Since the MPC prevents an overlap of the data and adress phase and /TS is only activ while the adress is activ on the bus, we should be able to safely latch the adress with the SRAM (doesn't matter if it is the CY7C1347G-166AXC or CY7C1441KV33) internally. As i mentioned before, the SRAM (CY7C1347G-166AXC and CY7C1441KV33) is able to latch the adress on the rising edge of the CLK, while /TS is asserted. In the end it worked over night without any issues at room temperature. Therefore i am conviced that the EBI works without an external latch.
Is there anything we don't see or we don't know, which requests the transparent latch as it is described in the EVB schematics?
