MPC5777C/e200z759 DCache Invalidation, L1CSR0 Access

[jeffcampbell]

Hello,

I'm performing Flash erase operations and have ended up needing to invalidate the D-Cache, because it holds data that should have been erased.

I'm fairly certain it's a cache problem, because the operation works fine with cache disabled entirely.  However, I'm hoping to just invalidate the cache so it can be still be used.

I'm working on the e200z759 core in a Greenhills environment.

Here's the code I'm trying to use, defined inside an asm function:

/** - Get current L1CSR0 value */
 mfspr r3,L1CSR0;

/** - Use R4 for mask (set bit 30) */
 e_lis r4,0x0000;
 e_ori r4,r4,0x0002;

/** - Apply mask */
 or r3,r3,r4;
 mtspr 1010,r3;
 se_isync;

When this code runs, it reads from L1CSR0 properly, but writing to it has no effect and I don't think it triggers an invalidation.  Is there something else I need to do to write to the register?

Thanks!

[davidtosenovjan · Accepted solution]

Hi, you try to look into following example code:

Example XPC567XRKIT PinToggleStationery CW210 

In the file Optimizations.c you may see how to initialize (invalidate) both caches. Note that is it applicable to MPC5777C device as it is partially backward compatible with MPC5676R and it uses same e200z759 core.

[jeffcampbell]

David,

I've checked out that example code and it looks like my logic is basically correct.  However, I'm following the execution of code step by step in the Greenhills debugger while viewing the L1CSR0 and L1CSR1 registers, and the instruction "mtspr L1CSR0, rX" does not set the Invalidate bit.  I've accessed the register in order to disable the cache entirely, and observed the bits changing in the register, but I haven't seen this work yet.  Do you have any ideas why it the L1CSR registers would resist a write to the invalidation bit?

Thanks,

Jeff

[jeffcampbell]

Actually, disregard this - it must not be possible to observe this happening in the register view, but I've checked the Cache explorer before and after the operation and it seems everything is being properly invalidated.  Never mind and thanks for the help!