[MPC5777C] Overlapping MMU Entries

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[MPC5777C] Overlapping MMU Entries

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ORaissouni
Contributor III

Hi Folks,

I have a question regarding the MMU setting in MPC5777C.
In case we have two MMU  entries which are overlapping(*), how would the MPC interpret these two entries ? Would they be perceived as contracting entries. or would they be somehow combined by the MPC ?

 

(*): Overlapping MMU entries here means, two MMU entries which are ruling/managing the same memory area but with different access rights.
Example:
        - TLB1 entry 5 =>  EPN:0x2501 0000,   Page Size: 1KB,    Access Right : R only,
        - TLB1 entry 6 =>  EPN:0x2501 0000,   Page Size: 1KB,    Access Right : W only,

 

With best Regards
Omar

 

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ORaissouni
Contributor III

Hi David,

Just read your reply.
Thank you so much for your inputs, there are very helpful.
In the end, we find out a way to fix the problem by setting up unique TLBs. 

With best regards
Omar

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ORaissouni
Contributor III

Hi David,

Thank you for your answer.
The case I gave was a just an example, just for the sake of understanding.
But actually, we want to set some generic MMU entries and then later on extend the rights when needed.

Back to my question, I did a quick test to check the MPC against overlapping MMU entries (incl. the example i gave before) and the test fails.
It seems, overlapping entries are NOT supported.
Then, I had a look into the core RM, here below a quotation from the core CM https://www.nxp.com/files-static/32bit/doc/ref_manual/e200z759CRM.pdf in 10.3.
" A hit to multiple TLB entries is considered to be a programming error. If this occurs, the TLB generates an invalid address but an exception will not be reported."

According to this quotation and the test i performed, overlapping MMU entries are not supported as it leads to an Invalid Real Address, could you please confirm or correct this conclusion ?

 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

Typical example where you can see multiple TLBs pointing to the same memory is default BAM MMU setting. TLB entry 2 (EBI) shows basically using of virtual address (logical base != physical base address) where TLB entry 1 points to the same physical address

davidtosenovjan_1-1677139940390.png

This is not a hit to multiple TLB entries and such configuration is possible. If it were otherwise, i.e one logical address would point to multiple physical address, such configuration would be a programming error. This is also needed to consider when user transits from one MMU configuration to another, to avoid conflict during this transition (when some TLB are added, other deleted and so).

 

 

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davidtosenovjan
NXP TechSupport
NXP TechSupport

In this case it would probably work, because according diagram below, an access would be granted separately for read and write.

davidtosenovjan_0-1677073289319.png

But, question is why you would do it this way. It is very unusual and common practice is to setup unique TLBs.

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ORaissouni
Contributor III

Hi David,

Just read your reply.
Thank you so much for your inputs, there are very helpful.
In the end, we find out a way to fix the problem by setting up unique TLBs. 

With best regards
Omar

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