MPC5777C BIST related question

[YounglaeKim]

Dear,

Based on the ERR010808, there's an issue regarding PLL Loss-of-Lock during offline BIST and the failure rate due to this issue is 0.02.

Does it mean the problematic situation will be occurred maximum 2 times when we do 100 times of offline BIST?

If it is right then the failure rate is too high to apply it to the mass production project.

Do you expect to apply this mechanism only to the project which allow this high failure rate?

If so, do you have any different recommended way for to use both MBIST and LBIST with shorten time?

Online MBIST + LBIST requires too long time so is it possible to use offline MBIST + online LBIST sequentially?

Could you please let me know the sequence to apply it?

Thank you.

[davidtosenovjan · Accepted solution]

I understand the erratum the way, that if PLL fails (it means source clock for the PLL, i.e. XOSC) during offline BIST, there is 2% probability that device does not get out of reset in case LBIST/MBIST offline BISTs are enabled and 0.02% probability for MBIST-only.

PLL failure rate is probably based on FMEDA. It is certainly not happen every POR sequence.

[YounglaeKim]

Thank you very much for your answer and let me clarify it.

Does the failure rate 0.02 mean 2% out of the PLL failure?

For example, if we have 0.02 failure rate of the PLL itself then the probabilty of the error due to the offline LBIST + MBIST will be 0.0004.

If so the final failure rate depends on the PLL failure rate of the oscillator what we are  using.

Is this right? Please let me know if I'm wrong.

[davidtosenovjan]

Yes, you are right.